KR940012665A - Double Gate Thin Film Transistor Structure and Manufacturing Method - Google Patents

Abstract

The present invention relates to a double gate thin film transistor to improve the switching speed by reducing the contact resistance and series resistance.

In a conventional thin film transistor, a semiconductor layer is formed on a gate, a source / drain electrode is formed on both sides of the semiconductor layer, and an n ⁺ semiconductor layer is formed between the source / drain electrode and the semiconductor layer.

In such a thin film transistor, the contact resistance and the series resistance become large, so that the loss of the driving current is large.

The present invention has a double gate structure, wherein a first gate electrode is formed on an insulating substrate, a semiconductor layer is formed on the first gate electrode, and a source / drain electrode is formed in a C shape on both sides of the semiconductor layer to surround a portion of the semiconductor layer. An ohmic contact layer is formed between the layer and the source / drain electrodes, and a second gate electrode is formed on the semiconductor layer.

Therefore, when a voltage is simultaneously applied to the first and second gate electrodes, two channels are formed in the semiconductor layer.

Therefore, the contact resistance and the series resistance are reduced, so that the switching speed is increased.

Description

Double Gate Thin Film Transistor Structure and Manufacturing Method

As this is a public information case, the full text was not included.

2 is a cross-sectional view of a double gate thin film transistor of the present invention.

3 is a process cross-sectional view of a double gate thin film transistor of the present invention.

Claims (3)

The insulating substrate 1, the first gate electrode 2a formed on the insulating substrate 1, the first insulating film 3 formed on the substrate 1 and the first gate electrode 2a, and the first insulating film ( 3) The source / drain electrode 6 formed on both sides with the semiconductor layer 4 interposed therebetween, and the ohmic contact layer 5a formed on the surface where the semiconductor layer 4 and the source / drain electrode 6 contact each other. , 5b), a second insulating film 7 formed over the source / drain electrode 6 and the semiconductor layer 4, and a second insulating film 7 formed over the first gate electrode 2a. A double gate thin film transistor structure comprising two gate electrodes (2b). Forming a first gate electrode 2a on the insulating substrate 1 and forming a first insulating film 3 on the front surface; depositing a metal on the first insulating film 3, and Patterning the first source / drain electrode 6a so that it remains, depositing the first ohmic contact layer 5a on the front side, and patterning it so that it remains only on the first source / drain electrode 6a; (4) and then depositing the ohmic contact layer 5b and defining an active region to remove unnecessary portions of the second ohmic contact layer 5b, the semiconductor layer 4, and the first ohmic contact layer 5b; Forming a second source / drain electrode 6b by depositing a metal on the entire surface and removing unnecessary portions of the channel portion; and using a second source / drain electrode 6b as a mask to form a second source / drain electrode 6b. Removing the ohmic contact layer 5b and forming a second insulating film 7 on the entire surface, and on the first gate electrode 2a. And forming a second gate electrode (2b) on the second insulating film (7). The method of manufacturing a double gate thin film transistor according to claim 2, wherein a high concentration of n-type micro-crystal silicon is used as the first and second ohmic contact layers (5a, 5b). ※ Note: The disclosure is based on the initial application.