KR940010673B1 - Low power data output buffer - Google Patents

Abstract

The buffer prevents the current consumption by a preset circuit, and is employed for the integrated semiconductor memory device. The buffer includes a 1st load trasistor (201) which supplies 1st power by 1st control signal, a 1st transmission transistor (203) which commonly connects control terminal and channel to an output node (N13), a 1st switching transistor (202) which switches 1st load and transmission trasistors (201)(203), a 2nd load transistor (204) which suppliies 2nd power by the 1st control signal, a 2nd switching transistor (205) which switches 2nd load and transmission trasistors (204),(206).

Description

Low Power Data Output Buffer

Embodiments 1a, b, c or prior art data output buffers.

2 is an embodiment of a data output buffer according to the present invention.

3 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a data output buffer of a memory device using an address transition detector (ATD).

The data output buffer is a device for inputting data read from the memory chip, amplifying the voltage, and outputting the data to the outside of the chip. Increasing the speed of operation due to the high integration of semiconductor memory devices is accompanied by a large noise. The main reason for this noise is a transition in a state in which a transistor provided at the output of the data output buffer has a large channel size. When the operation is performed, a large peak current is generated, which affects each power line in the chip, causing a large noise, thereby causing a malfunction of the semiconductor memory device. The reason why the impulse peak current occurs at the output stage of the data output buffer is that the channel size of the transistor constituting the output stage is considerably larger than that of other circuits, and that the ground voltage level at the power supply voltage level "high" This is because there is a full swing operation from "low" or from "low" to "high" level. Thus, in order to achieve low noise and speed-up, which are a requirement of the data output buffer, the output stage of the data output buffer has recently been changed from "high" to "low" level, or "low" to "high" level. Instead of performing the swing operation immediately, the intermediate level between the "high" and "low" levels (known in the art as "middle level" and hereinafter referred to as "middle level") is held in advance. A method of having a swing motion in a state has been proposed, and research on this is being conducted.

In this regard, a data output buffer circuit having a middle level conventionally presented is shown in FIG. The circuit shown in FIG. 1A is disclosed in detail in Japanese Unexamined Patent Publication No. Hei 1-49290 entitled "Output circuit of static RMA." 1A, the transistors M1 and M2 constitute an output driver stage, and the transistors m1 and m2 output the potential of the output line 7 carrying the output signal Dout of the data output buffer during data output operation. Transistors are made in advance to make the middle level. And the input signal S, Address transition detection circuit (not shown: this is a circuit for detecting the transition operation of an address, for example, in a device requiring fast access time and low power consumption such as static RAM or read only memory). A data signal under the control of the pulse signal outputted from /), which is data from a predetermined memory 쎌.

The operating characteristics according to this configuration are as follows. When a predetermined address is input, the input signal S, by the address transition detection circuit, Are all signals that are at the "low" level. From this the M1 and M2 transistors are both "turned off". Then, first, the case where the previous state of the output signal Dout is maintained at the "high" level. At this time, the output of the NAND gate 4 becomes " low " to turn on the m2 transistor. The m2 transistor then raises the gate voltage of the M2 transistor such that the M2 transistor is " turned on " (i.e., the output signal Dout remains at the middle level). At this time, the sizes of the m1 and m2 transistors are determined at the time of chip design so that the gate voltages of the M1 and M2 transistors are maintained at an intermediate level when fully turned on. The output signal Dout then has time to remain at the middle level. At this time, the input signal S and Becomes the "low" and "high" levels, respectively, the output of the inverter 1 controlling the gate voltage of the M1 transistor becomes "high" so that the M1 transistor is "turned off" and the gate voltage of the M2 transistor is controlled. The output of the inverter 6 becomes "high" so that the M2 transistor is "turned on" completely. Therefore, the output signal Dout is changed to the "low" level.

Next, the case where the previous state of the output signal Dout is maintained at the "low" level. At this time, the output of the NOA gate 2 becomes "high" and the m2 transistor is "turned on" (input signal S, The signals are each " low ", thereby dropping the gate voltage of the ml transistor ml transistor so that the M1 transistor is “turned on” midway. The output signal Dout then has time to remain at the middle level. At this time, the input signal S and When the signal goes to the "high" and "low" levels, respectively, the M2 transistor is "turned off" and the M1 transistor is completely "turned on". Therefore, the output signal Dout changes to the "high" level. As described above, the data output buffer like the first diagram performs the transition operation through the middle level without having a process of directly transitioning the output signal Dout from "high" to "low" or "low" to "high". Compared with other conventional circuits that perform the transition operation without going through the middle level, the generation of noise is reduced and the operation speed is also improved.

However, in the above-described first circuit, the channel of the m1 or m2 transistor is maintained by maintaining each gate voltage of the M1 and M2 transistors at a voltage level between the "high" and "low" levels to make the output signal Dout at the middle level. This leads to the generation of a direct current through. That is, the input signal S and When the output signal Dout is kept in a high state when all are "low", the m2 transistor is "turned on" by the "low" output of the NAND gate 4, wherein the inverter controlling the gate voltage of the M2 transistor Enmos transistor in (6) flows between the power supply voltage terminal (Vcc) and the ground voltage terminal (Vss) through the MOS transistor (each inverter of FIG. DC current flowing through the channel of M2 transistor and the channel of the transistor is generated. Similarly input signal S and When the output signal Dout is kept in a low state when the signals are all low, the m1 transistor is "turned on" by the "high" output of the NOA gate 2, which controls the gate voltage of the M1 transistor. DC current flowing between the power supply voltage terminal and the ground voltage terminal is generated through the PMOS transistor in the inverter 1. As described above, the circuit of FIG. 1 according to the related art has an effect of preventing the generation of the DC current generated at the output terminal of the conventional data output buffer. However, the circuit of FIG. It does not solve the fundamental problem of noise in the buffer and slowing down of operation speed.

On the other hand, another embodiment of precharging the voltage at the output stage is shown in FIG. 1b. FIG. 1b is proposed by Tomohisa wada et al. -22, NO. 5, OCTOBER 1987 "in detail entitled" A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon. " This configuration feature is characterized by the input trip level (or the threshold hold voltage) of the inverters I1 and I2 when the signal SAQ transitions from "high" to "low" or from "low" to "high". The difference causes the nodes 11 and 12 to have a time difference and to transition from "high" to "low" or "low" to "high" state, respectively, so that a signal of "high" state appears in node 15. The output node 19 is precharged or discharged to "turn on" the MOS transistors T1 and T2 during the pulse period of the node 15 so as to have a constant voltage value. However, in order to make the output node 19 connected to the input / output (I / O) terminal to a constant level for a sufficiently short time, the size of the N (N) transistor T1 and the P (P) transistor T2 should be large, in which case the NAND gate NA1 Since a direct current flows through the NMOS transistor T1, the PMOS transistor T2, and the NOA gate NO2, the current of the data output buffer is consumed. In addition, due to the difference in the input trip levels of the inverters I1 and I2 sharing the input, the outputs of the inverters I1 and I2 become "high" and "low", respectively, and are adjusted to the level of the output node 19 through the data bus. When the input trip level of the inverters I1 and I2 changes, the precharge time is changed, which adversely affects the operation speed. In addition, there is a disadvantage in that one more mask is required to make an inverter having different threshold voltages.

In order to solve this problem, another embodiment of the data output buffer conventionally presented is shown in FIG. 1C. The configuration shown in FIG. 1C is filed by the present applicant on October 25, 1991 under the title of "Data output buffer without DC current," which is disclosed in detail in Korean Application No. "91-18835". It is. The configuration characteristic of FIG. 1C is driven by the input stage using phi OE, which is a pulse signal generated by the address transition detection circuit, and the "high" and "low" of the DOUT output stage as inverters 33 and 34 connected to the DOUT output stage. The level is sensed to drive the pull-up stages 37 and 38 and the pull-down stages 39 and 40 for output. This prevents the generation of a direct current as in FIG. 1a and suppresses current consumption. However, under such a circuit configuration, the falling / rising time of the signal becomes considerably longer depending on the capacitance of the DOUT output stage. Current consumption is generated. In other words, when the chip is in the standby state or when the Φ OE pin is in the "high" state (i.e., not in the read operation), the voltage level of the DOUT output terminal may become an ambiguous level other than the "high" or "low" level. , Current consumption is generated in the inverters 33 and 34, respectively. In addition, when the voltage level of the N4 node and the N5 node "turns on" the transistors 38 and 39 in the standby state of the chip or the non-read operation, the power supply voltage terminal Vcc and the ground voltage terminal ( A DC pass is also formed between Vss).

On the other hand, it is well known in the art that general data output buffers including circuits such as the above-mentioned first a, b, c diagrams have a slower "low" level data output speed than "high" level data ( Specifically, for example, in the case of a mask ROM, the specification value is set to V _OL = 0.8 while V _OH = 2.0, so that the "low" level of the "high" level is set. The time for reading the data is later than the time for reading the data at the "low" level to the "high" level).

Accordingly, an object of the present invention is to provide a data output buffer with low power consumption.

Another object of the present invention is to provide a data output buffer in which formation of a DC path in itself is prevented.

It is still another object of the present invention to provide a data output buffer which prevents the generation of DC current in the standby state of the chip or in the non-read operation state.

It is still another object of the present invention to provide a data output buffer in which a DC current is prevented during active operation of a chip, thereby improving low noise and operating speed.

Still another object of the present invention is to provide a data output buffer which prevents the formation of a DC path in itself, thereby preventing the generation of a DC current at least in a standby state or during a write operation.

It is still another object of the present invention to provide a data output buffer for outputting data of "low" level at high speed.

The object of the present invention is a data output buffer having an output pull-up stage formed between the power supply voltage Vcc and the output node N13, and an output pull-down stage formed between the ground voltage Vss and the output node N13. The first load transistor 201 is connected to the power supply voltage Vcc and operated by a predetermined first control signal to supply a first load, and a control terminal and a channel are connected to the output node N13. When the voltage level of the output node N13 is sensed in common, the first transfer transistor 203 is pulled up when the detected voltage level is “low”, and is operated by a predetermined second control signal. A first switching transistor 202 for switching the first load transistor 201 and the first transfer transistor 203 and a channel connected to the ground voltage Vss and operated by the first control signal to operate a second load. 2nd supply A lower transistor 204 and a second transfer transistor 206 coupled to a control terminal and a channel at the output node to sense the voltage level of the output node and pull down when the sensed level is at a "high" level. And a channel connected between the second load transistor 204 and the second transfer transistor 206 by the second control signal to connect the second load transistor 204 and the second transfer transistor 206. It is achieved by providing a data output buffer, characterized in that it consists of a second switching transistor 205 for switching.

At this time, when a circuit consisting of each load transistor and each transmission transistor and switching transistor is functionally referred to as a "preset circuit", this is well known in the art. On the other hand, the pull-up song transistor and the pull-down transfer transistor according to the present invention operate complementary to each other, whereby the formation of the DC path is eliminated, thereby preventing the generation of the DC current and there is no part consuming the current. Low power data output buffer can be realized. In addition, it is obvious to those skilled in the art that each load transistor, each transfer transistor, and each switching transistor constituting the data output buffer according to the present invention can be implemented in various aspects. On the other hand, instead of the power supply voltage, the boosted voltage VPP employed in most of the semiconductor memory devices (which has a voltage level higher than the power supply voltage Vcc and is output in the same manner as a predetermined pumping circuit in the chip). May be used in place of the supply voltage.

Hereinafter, preferred embodiments of the present invention will be described in detail with the accompanying drawings. An embodiment of a data output buffer according to the present invention is shown in FIG. 3 illustrates an operation timing diagram according to the configuration of FIG. 2.

2 is a circuit for optimally realizing the spirit of the present invention. As can be seen from the configuration, the preset circuit according to the present invention is shown by a dotted block 200, which is commonly used in this field. The method is applied to the output buffer 110. The configuration of the preset circuit according to the present invention is as follows. That is, the preset circuit 200 according to the present invention has a power supply for a chip in the data output buffer 110 having an output pull-up end 106 and an output pull-down end 107 sharing the output node N13 with each other. A first load transistor 201 and an output node connected to a voltage terminal Vcc and operated by a predetermined chip select signal CS to supply a first load Vcc when a chip select operation occurs; The first transfer transistor connected to the control terminal and the channel at N13 detects the voltage level of the output node N13 during the standby state or the write operation of the chip, and pulls it up when the detected level is at the "low" level. 203 and a predetermined inverted output enable signal ( And a first switching transistor 202 that is operated by a channel and is connected between the first load transistor 201 and the first transfer transistor 203 to switch the first load and the first transfer transistor 201 (203). And a second load transistor 204 connected to the ground voltage terminal Vss of the chip and operated by the chip select signal CS to supply the second load Vss when the chip select operation occurs. And a control terminal and a channel are connected to the output node N13 to sense the voltage level of the output node N13 during the standby state or the write operation of the chip, and when the detected level is at the "high" level. The second transfer transistor 206 pulling down it and the inverted output enable signal ( And a second switching transistor 205 that is operated by a channel and is connected between the second load transistor 204 and the second transfer transistor 206 to switch the second load and the second transfer transistor 204 206. )

In this configuration, the chip select signal CS may be used as, for example, the output enable signal ΦOE, which is the first load transistor 201 and the first switching transistor 202, or the second load transistor 204. And the opening and closing operations of the second switching transistor 205 can be used as the same as the signal for operating complementary to each other. The output enable signal ΦOE is an output signal of the address transition detection circuit ATD circuit, and the input signal ( ) Is a signal output from the memory through the sense amplifier. In addition, as can be easily understood in this configuration, the opening and closing operation of the first transfer transistor 203 and the second transfer transistor 206 are complementary to each other to fundamentally prevent the generation of a DC current.

Operation characteristics according to the configuration of FIG. 2 are as follows. First, referring to the characteristics of each transistor of the preset circuit 200, the first load and the second load transistors 201 and 204 may have a stand-by state of the chip or an output enable signal. Since the operation is not performed in the "low" state (that is, not in the read operation), it serves to prevent the generation of the DC current according to the DOUT voltage of the output terminal N13. The first and second switching transistors 202 and 205 may include the inverted output enable signals generated by the address transition detection circuit after the address transition. ), It is " turned off " during operation of the chip and " turns on " for a predetermined time before moving on to the next operational state. The first and second transfer transistors 203 and 206 are transistors that are "turned on" or "turned off" by the DOUT voltage level of the output terminal N13. When the DOUT voltage level is "low" level, the first and second transfer transistors 203 and 206 are first transistors. When the transfer transistor 203 is "turned on" and the DOUT voltage level is "high" level, the second transfer transistor 206 is "turned on". Looking at the operation characteristics associated with the preset circuit 200 and the output buffer stage 110 according to this configuration as follows. When the address transitions, the output enable signal ΦOE transitions to "low", disabling the NOA gate 101 and the NAND gate 104, and the N11 and N12 nodes become "high" and "low", respectively. From the output pull-up driver 106 and pull-down driver 107 are " turned off ". The " turn off " operation of the output pull-up driver 106 and the pull-down driver 107 causes the DOUT voltage of the output node N13 to float to maintain the previous state. Input signal output from sense amplifier (not shown) When the next operation by is at the moment of reading the data in the opposite logic to the previous data, the DOUT voltage is full swing from "high" to "low" or "low" to "high".

However, by the preset circuit 200 according to the present invention, when the previous data level of DOUT is "low", the inverted output enable signal ( Transistors 201, 202, and 203 are " turned on " to precharge the output node N13 (in this case, a charging operation is performed). And when the previous data level of DOUT is " high, " Pull-down transistors 204, 205, and 206 are " turned on " to precharge the output node N13 (the discharge operation takes place at this time). This operation causes the voltage level of the output node N13 to be changed to the middle level in advance as in the prior art for the next read operation, thereby reading the data "low" or "high", thereby speeding up the data access time. It is to reduce the swing width of the and voltage. Also from this the access of the "low" data can be made at high speed. Therefore, in the data output buffer according to the present invention, the first load and the second load transistors 201 and 202 and the first and second switching transistors 204 and 205, respectively, in a non-read operation or in a standby state. Since it does not operate, generation of DC current or current consumption can be suppressed.

The preset circuit 200 as the second diagram according to the present invention is an optimal embodiment realized based on the idea of the present invention, but each transistor constituted is easily a transistor having a different channel by logic adjustment. It is obvious to those skilled in the art that this may be done. In addition, although the preset circuit 200 according to the present invention is used for the data output buffer 110 commonly used in this field, it is also obvious that it can be easily applied to data output buffers having other configurations.

As described above, the present invention includes a preset circuit having transistors having a switching operation complementary to each other in the data output buffer at pull-up and pull-down stages, respectively, regardless of the capacitance of the output node and not in the standby state or the read operation. It also prevents current consumption, providing a low-power data output buffer, especially suitable for ultra-high density semiconductor memory devices.

Claims (6)

A data output buffer having an output pull-up stage formed between a power supply voltage Vcc and an output node N13, and an output pull-down stage formed between a ground voltage Vss and the output node N13. Vcc) is connected to the first load transistor 201 and a first load transistor 201 is supplied by a predetermined first control signal to supply a first load, and the control terminal and the channel is commonly connected to the output node (N13) the output node After sensing the voltage level of N13, when the detected voltage level is in the "low" state, the first transfer transistor 203 pulls it up, and is operated by a predetermined second control signal and is operated by the first load transistor 201. ) Is connected between the first transfer transistor 203 and the first switching transistor 202 for switching the first load transistor 201 and the first transfer transistor 203 and the ground voltage Vss. The channel is connected and said A second load transistor 204 operated by a first control signal to supply a second load, and a control terminal and a channel are connected to the output node to sense a voltage level of the output node and the detected level is " high " A second transfer transistor 206 that pulls it down when it is at a level, and is operated by the second control signal and a channel is connected between the second load transistor 204 and the second transfer transistor 206 so that the second transfer transistor 206 pulls it down. And a second switching transistor (205) for switching the two load transistors (204) and the second transfer transistor (206). The data output buffer according to claim 1, wherein the first load and the second load are a power supply voltage (Vcc) and a ground voltage (Vss), respectively. 3. The inverted output enable signal of claim 2, wherein the first control signal is a chip select signal CS, and the second control signal is an inverted output enable signal output from an address transition detection circuit in the chip. Data output buffer characterized in that). 4. The data output buffer as recited in claim 3, wherein said first and second load transistors comprise at least a write operation or a disable operation in a standby state of the chip. 5. The data output buffer as claimed in claim 3 or 4, wherein the first and second switching transistors are deactivated at least in a write operation or a standby state of the chip. The data output buffer according to claim 1, wherein the opening and closing operations of the first transfer transistor and the second transfer transistor are complementary to each other according to the voltage level of the output node.