KR940007846A - Synchronization signal control circuit of digital data - Google Patents

Synchronization signal control circuit of digital data Download PDF

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Publication number
KR940007846A
KR940007846A KR1019920016847A KR920016847A KR940007846A KR 940007846 A KR940007846 A KR 940007846A KR 1019920016847 A KR1019920016847 A KR 1019920016847A KR 920016847 A KR920016847 A KR 920016847A KR 940007846 A KR940007846 A KR 940007846A
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KR
South Korea
Prior art keywords
synchronization signal
synchronization
data
signal
digital data
Prior art date
Application number
KR1019920016847A
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Korean (ko)
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KR0186029B1 (en
Inventor
우상준
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920016847A priority Critical patent/KR0186029B1/en
Publication of KR940007846A publication Critical patent/KR940007846A/en
Priority to US08/400,510 priority patent/US5682457A/en
Application granted granted Critical
Publication of KR0186029B1 publication Critical patent/KR0186029B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 디지탈 데이타의 동기 신호 제어에 관한 것으로, 일반적으로 사용되고 있는 디지탈 데이타 재생 회로는 유효 데이타와 더미 데이타의 동기 블록을 판별하기 위해 서로 상이한 형태의 동기 블록을 형성함으로 기록 포맷을 맞추기 위한 회로가 복잡해지고, 재생시에도 유효 데이타 블록과 더미 데이타 블록을 판별하기 위한 회로가 부가되므로 복잡한 회로가 필요하게 되는 문제점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the control of synchronization signals of digital data. In general, digital data reproducing circuits have circuits for matching recording formats by forming different types of synchronization blocks to discriminate sync blocks of valid data and dummy data. There is a problem that a complicated circuit is required since the circuit for discriminating the effective data block and the dummy data block is added even during reproduction.

이에 따라 본 발명의 목적은 상기와 같은 종래의 디지탈 데이타의 동기신호 제어회로에 따르는 결함을 해결하기 위하여, 재생시 검출되는 동기 신호중 동기신호를 계수하여 더미 데이타 동기 블록의 동기신호를 억제하고 유효 데이타 동기 블록만을 추출하는 동기신호 검출회로를 제공하는데 있다.Accordingly, an object of the present invention is to counteract the synchronization signal of the dummy data synchronization block by counting the synchronization signal among the synchronization signals detected at the time of reproduction in order to solve the defect caused by the conventional synchronization signal control circuit of digital data. A synchronization signal detection circuit for extracting only a synchronization block is provided.

Description

디지탈 데이타의 동기신호 제어회로Synchronization signal control circuit of digital data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 디지탈 데이타의 동기신호 제어회로도.3 is a synchronization signal control circuit diagram of the digital data of the present invention.

Claims (1)

재생신호로부터 동기신호를 검출하는 동기 검출부(100)와, 상기 동기검출부(100)에 의해 검출된 동기신호를 클럭입력으로하여 헤드 스위칭 신호로부터 일정 시간을 계수하여 그 계수값에 따라서 입력된 동기신호가 유효데이타의 동기클럭인지 더미 데이타의 동기 클럭인지를 구분하고 그에 따른 신호를 출력하는 카운터(120)와, 상기 동기 검출부(100)로부터의 동기신호 및 데이타를 일정 시간동안 지연시키는 지연부(110, 130)와, 상기 지연부(110) 및 카운터(120)의 출력을 논리조합하여 더미 데이타의 동기신호를 억제하고 유효 데이타의 동기신호만을 출력하는 게이트부(140)와, 상기 게이트부(140)의 유효 동기신호를 입력받아 상기 지연부(130)의 출력신호로부터 원래의 재생 데이타를 출력하는 재생 포맷터(150)를 포함하여 구성한 것을 특징으로 하는 디지탈 데이타의 동기신호 제어회로.A synchronization signal 100 for detecting a synchronization signal from the reproduction signal, and a synchronization signal detected by the synchronization detection unit 100 as a clock input, counting a predetermined time from the head switching signal, and inputting the synchronization signal according to the count value. A counter 120 for distinguishing whether a synchronous clock is a synchronous clock of the valid data or a synchronous clock of the dummy data and outputting a signal according to the delay time; 130 and the gate unit 140 which logically combines the outputs of the delay unit 110 and the counter 120 to suppress the synchronization signal of the dummy data and output only the synchronization signal of the valid data, and the gate unit 140. And a reproducing formatter 150 for receiving the effective synchronizing signal and outputting the original reproducing data from the output signal of the delay unit 130. Itaconic synchronizing signal control circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920016847A 1992-02-15 1992-09-16 Circuit for controlling a synchronized signal of the digital data KR0186029B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920016847A KR0186029B1 (en) 1992-09-16 1992-09-16 Circuit for controlling a synchronized signal of the digital data
US08/400,510 US5682457A (en) 1992-02-15 1995-03-07 Method and apparatus for recording HDTV signals having a wide bandwidth on a narrow bandwidth tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920016847A KR0186029B1 (en) 1992-09-16 1992-09-16 Circuit for controlling a synchronized signal of the digital data

Publications (2)

Publication Number Publication Date
KR940007846A true KR940007846A (en) 1994-04-28
KR0186029B1 KR0186029B1 (en) 1999-04-15

Family

ID=19339619

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920016847A KR0186029B1 (en) 1992-02-15 1992-09-16 Circuit for controlling a synchronized signal of the digital data

Country Status (1)

Country Link
KR (1) KR0186029B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571566A (en) * 1994-03-10 1996-11-05 Union Steel Manufacturing Co., Ltd. Method of manufacturing a coated steel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571566A (en) * 1994-03-10 1996-11-05 Union Steel Manufacturing Co., Ltd. Method of manufacturing a coated steel

Also Published As

Publication number Publication date
KR0186029B1 (en) 1999-04-15

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