KR920008113B1 - Detecting apparatus for error generating rate of each track - Google Patents

Abstract

The circuit detects the error rates by tracks to reproduce the tape. The circuit comprises: a counting means consisting of two inverters (I1,I2), an AND gate (G1), three NAND gates (N1-N3) and a counter (10) to count the number of errors produced in each track; a latching means, consisting of two AND gates (G2,G3), an inverter (I3) and two latching circuit (11,12), for dividing the output of the counting means by tracks; and a compartor (13) for detecting the change of the error rate in each track by comparing the outputs of the latching means.

Description

Track error detection rate device

1 is a circuit diagram of the present invention.

2 is an operational waveform diagram for FIG.

* Explanation of symbols for main parts of the drawings

10: counter 11, 12: latch circuit

13 comparator N1-N3 negative logic device

G1-G3: logical multiplication device I1-I3: inverting device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting an error occurrence rate in a digital audio tape recorder (hereinafter referred to as R-DAT) in order to extract information on the stability of a system when reproducing information recorded on a tape.

In general, R-DAT refers to a device for recording audio information in a digital form on a tape or reproducing digital information on a tape. The R-DAT reproducing operation reads the digital data recorded on the tape, corrects the read digital data in error, and converts the digital data into an analog form for transmission through the speaker. However, if the tape is damaged or dusty, you may not be able to reproduce the correct information, and errors may also occur due to inaccurate tracking of each track on the tape or noise on the system.

Conventionally, there is a problem that a user cannot adjust the system to reproduce correct voice information because a detection device for detecting such an error is not installed in the R-CAT. Therefore, when an error occurs in the R-DAT, in order to reproduce correct voice information, it is natural that the error cannot be corrected by using an auxiliary device or the track of each track of the tape can be accurately tracked by using a servo device. Therefore, the above problem can be solved if there is a device that can detect information on the error occurrence rate and the degree of change, which is a criterion for adjusting the degree of error correction or the precision of the servo.

Accordingly, an object of the present invention is to provide an apparatus capable of detecting the error occurrence rate and the change degree of each track of a tape required for adjusting the degree of error correction and tracking in R-CAT.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of the present invention, which includes a coding and decoding unit for error correcting information read from a tape and generating an error flag signal whenever an error occurs, and generating a count clock and error correction control signal and a frame synchronization signal as a reference clock. In an R-DAT having a divider circuit, a track combination is performed by logically combining and counting an error flag signal extracted from the coding and decoding unit, a count clock sequence and an error correction control signal and a frame synchronization signal extracted from the divider circuit. A counting means comprising a counter 10, an AND multiplication element G1, two inverting elements I1, I2, and three negative logic elements N1-N3 for counting the number of error occurrences, and drawing out from the frequency division circuit. Two logical multiplications for classifying the output of the counting means by tracks according to the error correction control signal and the frame synchronizing signal to be output to each output port. A comparator 13 for detecting a change in the error occurrence rate between tracks by comparing the latch means consisting of (G2, G3) and the latch circuits (11, 12) and the inverting element (I3) with the output of the output ports of the latch means. ).

2 is an operation waveform diagram of FIG. 1, wherein 20 is a frame synchronization signal, 21 is an error correction control signal, and 22 is a count clock sequence.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. The frame synchronizing signal and the error correction control signal and the count clock string generated from the not-shown division circuit are supplied on the three lines (.L1-L3), and the frame synchronizing signal and the error correction control signal and the count clock string will be described. As follows.

The frame synchronization signal is the same as that of FIG. 20. In FIG. 20, the head scans the track A of the tape in the high logic period, and the track B tracks the tape in the low logic state of FIG. Scan. The error correction control signal is as shown in FIG. 21, and the period T12 in the high logic state is a period during which the coding and decoding unit error corrects data read from the tape by the head every track. The count clock sequence is as shown in FIG. 22, and there are 128 pulse sequences in the high logic state section T12 of the error correction control signal. Therefore, the coding and decoding unit performs 128 error correction operations during the high logic state period of the error correction control signal. If an error occurs, the coding and decoding unit generates a high logic error flag signal and supplies it on the line L4. The error correction operation of the coding and decoding unit is performed in a predetermined period T34 from the time t3 to the time t4 in the low logic state period of the count clock sequence as shown in FIG. 22, when an error occurs The coding and decoding unit generates an error flag that maintains the high logic state from the time t5 during the low logic state period of the count clock sequence as shown in FIG.

The negative logic element N1 performs a negative logic operation on the frame synchronization signal, the error correction control signal, the count clock sequence, and the error flag signal on the four lines L1 to L4 so that the logic states of the four signals are all high logic. In the state, an output signal having a low logic state is supplied to one input terminal of the negative logic element N3. The negative logic element N2 performs a negative logic operation on the frame synchronization signal introduced through the inversion element I1, the error correction control signal on the thin lines L2-L4, the count clock string, and the error flag signal. When all four input signals are in a high logic state, an output signal having a low logic state is supplied to the other input terminal of the negative logic element N3.

The negative logic element N3 performs a negative logic operation on the outputs of the two negative logic elements N1 and N2 and supplies the negative logic unit N3 to the clock terminal CLK of the counter 10. Then, when an error occurs, when the error correction control signal is in the high logic state and the frame synchronizing signal is in the high or low logic state, the output of the negative logic element N3 becomes the same as the count clock string so that the falling edge of the count clock is falling. In the counter 10 is an addition count operation. The counter 10 counts up at the falling edge, which will be described. Since up to 128 error flag signals can be generated in the section in which the error correction control signal C1-AREA is in the high logic state, that is, in the error correction working section, the counter 10 has 7-bit output terminals and the clear terminal ( Cleared when high logic state is inputted to CLR). The output of the counter 10 is a signal indicating how many blocks an error has occurred during error correction.

In addition, when it is necessary to know whether the error occurrence value for the A track or the error occurrence value for the B track is required, it can be displayed in combination with the frame synchronization signal as appropriate.

When the output of the logical multiplication device G1 is in a high logic state, the counter 10 is cleared. The logical multiplication device G1 has a high logic when the error correction control signal is in a low logic state and the count clock is in a high logic state. Output the status. Since the error flag signal is in the low logic state when the error correction control signal is in the low logic state, the counter 10 does not operate. Therefore, the counter 10 is always cleared when the error correction control signal is in the low logic state. Can operate normally.

The two latch circuits 11 and 12 include seven D flip-flops each of which can operate at the falling edge, and the clock terminals CLK are shared.

The latch circuit 11 operates when the output of the AND product G2 is the falling edge, and the latch circuit 12 operates when the AND device G3 is the falling edge to latch the output of the counter 10. .

Since the output of the logical multiplication device G2 outputs an error correction control signal when the frame synchronization signal is in a high logic state, the error correction control signal when the counter 10 counts all the numbers after correcting the error in track A. Has a falling edge at the same time that it changes from a high logic state to a low logic state.

On the other hand, the output of the logical multiplication device G3 outputs an error correction control signal when the frame synchronization signal is in a low logic state. Therefore, the error correction control is performed when the counter 10 counts all the numbers after correcting the error in the track B. It has a falling edge at the same time that the signal changes from the high logic state to the low logic state.

Therefore, it can be seen that the latch circuit 11 latches the number of error flags generated in the track A and the latch circuit 12 latches the number of error flags generated in the track B.

The comparator 13 compares the number of error occurrences of the A and B tracks, which are introduced into the first and second input ports from the two latch circuits 11 and 12, respectively, and compares the two output terminals AEQB and AGTRTHB according to the magnitude. Determine and output the logic value.

The first output terminal AEQB of the comparator 13 is in a high logic state when the number of error occurrences of the track A is equal to the number of error occurrences of the track B, and the second output terminal AGTRTHB of the comparator 13 is A. If the number of error occurrences of the track is larger than the number of error occurrences of the track B, the state becomes high logic.

Here, the outputs of the first and second output terminals are applied to and displayed on the display unit of the system, and in the case of a tape having a high probability of error occurrence, the error is corrected using an auxiliary device or precisely using a servo device. By adjusting or changing each track of the tape to be tracked, it is possible to reproduce voice information with less error.

As described above, the present invention has an advantage in that, in R-DAT, an error occurrence of data read from the tape can be detected on a track-by-track basis, and a track-specific change in error occurrence can be detected.

Claims (1)

R--DAT including a coding and decoding unit for error correction of information read from the tape and generating an error flag signal whenever an error occurs, and a division circuit for counting and error correction control signals and frame synchronization signals for the reference clock. Counting means for counting the number of error occurrences per track by logically combining and counting the error flag signal drawn from the coding and decoding unit, the count clock string and the error correction control signal and the sync synchronization signal drawn from the frequency divider circuit; (I1, I2, G1, N1-N3, 10) and the output of the counting means for each track by classifying the output of the counting means by the error correction control signal and the frame synchronizing signal connected to the counting means and drawn out from the frequency division circuit. The latch means (I3, G2, G3, I1, I2) leading to the port and the output of the output port of the latch means connected to the latch means are compared with each other And a comparator (13) for detecting a change in the error occurrence rate between tracks.

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