KR940006558Y1 - Apparatus for stabilizing osd signals - Google Patents

Abstract

No content.

Description

OSD Stabilization Circuit

1 is an OSD stabilization circuit according to and.

* Explanation of symbols for main parts of the drawings

10: integrated circuit for synchronous separation 20: switching unit

30: integrated circuit for character generation 40: control unit

TR1 ~ TR6: Transistor

This design relates to a video tape recorder, and more particularly, it substitutes a vertical sync signal based on head switching in the microcomputer instead of a vertical sync signal separated from a special playback mode video signal such as a still mode or a search mode. The present invention relates to an OSD stabilization circuit that stabilizes an OSD (On Screen Desplsy) phase by using a single signal.

In general, the synchronous separation integrated circuits used in modern times do not ensure vertical synchronous separation in special playback modes such as steel and large noise bars, so that the integrated circuit for character generation is a vertical synchronous signal. As it is recognized, there is a problem that the OSD characters bounce up and down due to synchronous anxiety, and thus the OSD characters are not stable.

This invention solves this problem. The purpose of this invention is to use a signal that can be used instead of the vertical synchronization signal based on the headswitching that occurs in the microcomputer instead of the vertical synchronization signal separated from the video signal in the special playback mode. It is to provide an OSD stabilization circuit that can provide a clear picture by stabilizing the OSD characters.

The feature of the OSD stabilization circuit according to the present invention for achieving this object is an OSD stabilization circuit having a synchronous separation integrated circuit for separating the synchronization of the input video signal, and an integrated circuit for generating a character generating OSD characters In this case, the vertical synchronization signal is used as a substitute for the JOG IN signal which is high during video playback and low when normal playback, and the head muting signal input from the microcomputer in video mute and jog mode. And a control unit which is operated by inputting a JOG VD signal and a switching unit which is connected to the synchronous separation integrated circuit and is switched from the synchronous separation integrated circuit according to horizontal and vertical synchronization signals.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is an OSD stabilization circuit diagram according to Io, and connects the switching unit 20 to an synchronous separation integrated circuit 10 that separates an input video signal into horizontal and vertical synchronous signals.

The switching unit 20 includes switching transistors TR4 and TR5 switched according to the horizontal and vertical synchronization signals H SYNC and V SYNC from the synchronous separation integrated circuit 10. .

In addition, the switching unit 20 generates OSD characters according to the logic signal from the switching unit 20 and the strobe signal which is an OSD data signal, a clock signal, and a data input reference recognition signal according to the control of the microcomputer. 20 Connect the circuit.

In addition, the vertical synchronization signal output port VP and the switching unit 20 of the synchronous separation integrated circuit 10 are connected to a control unit 40 for controlling the switching unit 20 to stabilize the OSD image.

The control unit 40 is connected to the jog signal input terminal JOG IN, and the emitter side is connected to a signal (JOG VD) input terminal (a), which is connected to the base side of the jog signal input terminal and can be used for the vertical synchronization signal band based on the head switching in the special playback mode. Is connected to the " turned on " during the special playback mode so that the signal (JOG VD), which can be used as a substitute for the vertical synchronization signal based on the head switching in the special playback mode, is applied to the switching unit 20 to generate the character. The switching transistor TR1 for controlling the integrated circuit 30 and a base axis are connected to the video mute stage b, and a collector side is connected to the base side of the transistor TR1, thereby being turned on during video muting. The base axis is connected to the switching transistor TR2 and the jog signal input terminal JOG IN, and the emitter side is connected to the vertical synchronous signal output terminal VP of the synchronous separation integrated circuit 10 so that a normal regeneration mode is used. Is turned on "is composed of a switching transistor (TR3) for controlling said switching unit (20).

In Fig. 1, the jog input signal JOG IN is high during special playback of the video tape recorder, and low during normal playback. In addition, the video mute signal becomes high when there is no video signal input, and the JOG IN signal is held low because the OSD operates unstable in the video mute mode while in the JOG mode.

When the video signal is input to the synchronous separation integrated circuit 10 in the above-described scheme, the video signal is separated into a horizontal synchronous signal H SYNC and a vertical synchronous signal V SYNC in the synchronous separation integrated circuit 10. Output via the vertical synchronous signal output port VP and the horizontal synchronous signal output port HP, respectively.

First, since the logic "logic" is input to the jog signal input terminal JOG IN input under the control of the microcomputer in the normal reproducing mode, the transistor TR1 is "turned off" and the transistor TR3 is "turned on" to synchronize the synchronization. The vertical synchronization signal from the vertical synchronization signal output port VP of the isolation integrated circuit 10 controls the base terminal of the transistor TR4 of the switching unit 20 through the transistor TR3.

Accordingly, the vertical synchronization signal inverted from the collector side of the transistor TR4 is input to the character generation integrated circuit 30 to be a reference signal for character generation.

Similarly, the horizontal synchronization signal from the horizontal synchronization signal output port HP of the synchronization isolation integrated circuit 10 controls the base end of the transistor TR5 and is inverted from the collector side of the transistor TR5. A signal is input to the character generation integrated circuit 30 to be a signal of character generation.

On the other hand, between the search mode and the steel mode, a logic "high" is applied to the jog signal input terminal JOG IN during a special reproduction mode, so that the transistor TR1 is "turned on" and thus the transistor TR2 is "turned off". .

In this case, when there is a screen mute at the beginning of the special playback mode, the de- mute signal becomes a logic "high", so a logic "high" is applied to the video mute stage b. During this period, the transistor TR3 is "turned on" and the video As the transistor TR2 connected to the mute terminal b is "turned on", when the video muting is released after a certain time has elapsed, the transistor TR1 is "turned on" and the transistor TR3 is "turned on". In the OFF state, a signal (JOG IN), which enables the microcomputer to use the vertical synchronization signal band based on the head switching in the special regeneration mode, is input to the input terminal a and the collector to the transistor TR4 through the transistor TR1. Inverted at the side, character generation is input to the integrated circuit 30.

The character generation integrated circuit 30 receives an OSD data signal, a clock signal, and a strobe signal from a microcomputer, and is inverted from the collector side of the transistors TR4 and TR5, and is inputted as a horizontal synchronous signal H SYNC. OSD characters are generated and displayed on the screen according to the synchronization signal V SYNC. The output OSD signals are mixed with the video signal and displayed on the screen.

As described above, this design generates a signal that can be used as a substitute for vertical sync signal based on the head switching in the microcomputer, and uses it instead of the vertical sync signal in the special playback mode. When the noise component is used as a vertical synchronization signal, the OSD unstable state that occurred when the clear screen can be seen.

Claims (2)

An OSD stabilization circuit having a synchronization isolation integrated circuit (10) for separating synchronization of an input video signal and a character generation integrated circuit (30) for generating OSD characters, wherein the OSD is in a high state during special playback of a video tape. In normal playback, the control unit operates by inputting JOG IN signal in a low state and JOG VD signal using a vertical synchronous signal as a substitute for a video mute signal and a head switching signal input from a microcomputer in the jog mode. And a switching unit (20) connected to the synchronous separation integrated circuit (10) and switched according to horizontal and vertical synchronization signals from the synchronous separation integrated circuit (10). The signal of claim 1, wherein the control unit 40 has a base connected to the jog signal input terminal JOG IN, and allows a special playback mode to be used as a substitute for the vertical synchronization signal based on the head switching in the microcomb during the special playback mode. The emitter side is connected to the input terminal a and is turned on in the special regeneration mode to control the switching unit 20, and the base side is connected to the video mute terminal b. A switching transistor TR2 connected to the base side of the transistor TR1 and " turned on " when the video is muted, and a base side connected to the jog signal input terminal JOG IN and the synchronization side integrated circuit 10 An OSD stability circuit comprising a switching transistor (TR3) for controlling the switching unit 20 is connected to the emitter side of the vertical synchronous signal output terminal (VP) and is "turned on" during the normal reproduction mode.