KR940004600B1 - Method of fabricating a dram cell and structure thereof - Google Patents

Method of fabricating a dram cell and structure thereof Download PDF

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Publication number
KR940004600B1
KR940004600B1 KR1019910011918A KR910011918A KR940004600B1 KR 940004600 B1 KR940004600 B1 KR 940004600B1 KR 1019910011918 A KR1019910011918 A KR 1019910011918A KR 910011918 A KR910011918 A KR 910011918A KR 940004600 B1 KR940004600 B1 KR 940004600B1
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polysilicon
film
forming
word line
oxide
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KR1019910011918A
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Korean (ko)
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KR930003385A (en
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김익년
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

sequentially depositing a first oxide and nitride on a substrate, and forming a contact hole between a wordlines; depositing a first polysilicon on a portion from the bottom of the contact hole to a predetermined height of the nitride, and forming a second oxide and second polysilicon layer; forming a second oxide/second polysilicon layer block having a predetermined width above the wordlines; forming a sidewall polysilicon layer on the side of the block; removing the second oxide to form a storage node polysilicon layer; and forming a dielectric layer on the surface of the storage node polysilicon layer, and depositing a plate polysilicon, thereby increasing the capacitance of DRAM and improving the step coverage.

Description

디램 셀 제조방법 및 구조DRAM cell manufacturing method and structure

제1도는 종래의 제조공정 단면도.1 is a cross-sectional view of a conventional manufacturing process.

제2도는 본 발명의 제조공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 워드라인1: silicon substrate 2: word line

3 : 제1산화막 4 : 질화막3: first oxide film 4: nitride film

5 : 제1폴리실리콘막 6 : 제2산화막5: first polysilicon film 6: second oxide film

7 : 제2폴리실리콘막 8 : 제3폴리실리콘막7: second polysilicon film 8: third polysilicon film

8a : 측벽폴리실리콘막 9 : 커패시터 유전체막8a: sidewall polysilicon film 9: capacitor dielectric film

10 : 플레이트 폴리실리콘막10: plate polysilicon film

본 발명은 디램 셀(DRAM CELL)에 관한 것으로, 특히 커패시터 형성방법 및 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM cells, and more particularly, to a method and structure of capacitor formation.

종래 디램 셀을 제조하기 위한 일 공정을 첨부된 제1도(a) 내지 제1도(g)를 참조하여 설명하기로 한다.One process for manufacturing a conventional DRAM cell will be described with reference to FIGS. 1A to 1G.

본 발명은 디램 셀 중 커패시터 형성에 관한 것이므로 제1도(a)와 같이 기판(11)상에 게이트 산화막(12) 및 워드라인(word line)(13)을 포함한 모스 트랜지스터(Mos Transistor)제조과정의 설명은 생략하기로 한다.Since the present invention relates to the formation of capacitors in DRAM cells, a process of manufacturing a MOS transistor including a gate oxide film 12 and a word line 13 on a substrate 11 as shown in FIG. The description of will be omitted.

먼저 제1a도와 같이 커패시터를 형성하기 위해 전체적으로 산화막(14)(SiO )과 질화막(Si3N4) (15) 및 산화막(16)을 차례로 증착한다.First, as shown in FIG. 1A, an oxide film 14 (SiO), a nitride film (Si 3 N 4 ) 15, and an oxide film 16 are sequentially deposited to form a capacitor.

제1b도와 같이 사진 및 식각공정을 거쳐 상기 게이트 산화막(12)과 산화막(14,16) 및 질화막(150)을 소정폭만큼 에치함으로써 워드라인 사이에 콘택트 홀을 형성한 다음 상기 산화막(16)의 표면위로 소정 두께만큼 폴리실리콘막(17)을 증착한다.As shown in FIG. 1B, the gate oxide layer 12, the oxide layers 14, 16, and the nitride layer 150 are etched by a predetermined width through a photolithography and etching process to form a contact hole between the word lines, and then, as shown in FIG. The polysilicon film 17 is deposited on the surface by a predetermined thickness.

이어 제1d도와 같이 전체적으로 폴리실리콘막을 증착한 다음 RIE(Reactive Ion Etching)공정을 수행하여 상기 폴리실리콘막(19)과 산화막(20)의 측면에 측벽폴리실리콘막(21)을 형성한다.Subsequently, a polysilicon film is deposited as a whole as illustrated in FIG. 1d and then a reactive ion etching (RIE) process is performed to form the sidewall polysilicon film 21 on the sides of the polysilicon film 19 and the oxide film 20.

이때 상기 폴리실리콘막(17)중 측벽 폴리실리콘막(21)을 벗어나는 부분은 함께 제거되며 측벽 폴리실리콘막(21)의 피크 부분은 산화막(20)두께의 중간 부분에 위치되도록 형성한다.In this case, portions of the polysilicon layer 17 that deviate from the sidewall polysilicon layer 21 are removed together, and a peak portion of the sidewall polysilicon layer 21 is formed to be positioned at an intermediate portion of the thickness of the oxide layer 20.

이어 제1e도와 같이 상기 산화막(20)상에 사진 및 식각 공정을 실시하여 상기 콘택트 홀(Contact hole)상의 산화막(20)과 폴리실리콘막(19)을 동일 폭만큼 제거함으로써 스토리지 노드속의 산화막(18)을 에치해내기 위한 윈도우(Window)를 형성한다.Subsequently, as shown in FIG. 1E, a photolithography and an etching process are performed on the oxide layer 20 to remove the oxide layer 20 and the polysilicon layer 19 on the contact hole by the same width, thereby forming the oxide layer 18 in the storage node. Create a window to etch).

그리고 제1f도와 같이 산화막 에쳔트인 HF용액속에 디핑(dipping)시킴으로써 상기 윈도우를 통해 스토리지 노드속의 산화막(18) 및 산화막(16)을 제거한다.As shown in FIG. 1F, the oxide film 18 and the oxide film 16 in the storage node are removed through the window by dipping into an HF solution that is an oxide film.

따라서 스토리지 노드 폴리실리콘막이 완성된다.Thus, the storage node polysilicon film is completed.

그리고 제1g도와 같이 상기 스토리지 노드 폴리실리콘막 표면에 유전체막(22)을 도포한 다음 그 위에 플레이트 폴리실리콘막(23)을 형성함으로써 공정이 완료된다.The process is completed by applying the dielectric film 22 to the surface of the storage node polysilicon film as shown in FIG. 1g and then forming the plate polysilicon film 23 thereon.

상기 종래 기술은 제조 기술상에는 문제가 없으나 단지 구조상 커패시터 용량의 확대여지가 많으나 이를 충분히 활용치 못한 단점이 있었다.The prior art has no problem in manufacturing technology, but there is a lot of room for expansion of the capacitor capacity, but there is a disadvantage in not fully utilizing it.

본 발명은 상기 단점을 제거키 위한 것으로, 커패시턴스 용량을 증대시킬 수 있는 하이그레이드(high grade)소자의 제조에 적당한 디램 셀 제조공정을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention aims at eliminating the above disadvantages, and an object of the present invention is to provide a DRAM cell manufacturing process suitable for manufacturing a high grade device capable of increasing capacitance capacity.

상기 목적을 달성하기 위하여 워드라인 및 소오스, 드레인 형성이후 진행되는 디램 셀 제조공정에 있어서, 제1산화막과 질화막을 차례로 증착한 후 에치공정을 거쳐 워드라인 사이의 소오스영역에 콘택트 홀을 형성하기 위한 스텝, 상기 콘택트 홀이 메꾸어지도록 상기 질화막상으로부터 소정두께만큼 제1폴리실리콘막을 증착하고 그 위에 제2산화막과 제2폴리실리콘막을 차례로 증착하는 스텝, 각 워드라인 상측부분을 제외하곤 제2산화막 및 폴리실리콘막을 제거하여 각 워드라인 상측부분에 산화막/폴리실리콘막 블럭을 형성하는 스텝, 제3폴리실리콘막을 증착한 후 에치하여 각 블럭 측면에 측벽 폴리실리콘막을 형성하는 스텝, 제2폴리실리콘막과 측벽 폴리실리콘막으로 둘러쌓인 상기 블럭중의 제2산화막을 제거하여 스토리지 노드 폴리실리콘막을 완성하는 스텝, 상기 스토리지 노드 폴리실리콘의 표면에 커패시터 유전체막 및 플레이트 폴리실리콘막을 차례로 형성하는 스텝이 차례로 포함된다.In order to achieve the above object, in the DRAM cell fabrication process which is performed after the formation of the word line, the source and the drain, the first oxide film and the nitride film are sequentially deposited and then etched to form contact holes in the source region between the word lines. And depositing a first polysilicon film on the nitride film by a predetermined thickness so that the contact hole is filled, and then depositing a second oxide film and a second polysilicon film thereon, a second oxide film except for an upper portion of each word line; Removing the polysilicon film to form an oxide film / polysilicon film block on the upper portion of each word line, depositing a third polysilicon film, and then etching the polysilicon film to form a sidewall polysilicon film on each side of the block; The storage node polysilicon film is removed by removing the second oxide film in the block surrounded by the sidewall polysilicon film. The completing step, the step of forming the storage node polysilicon surface of the capacitor dielectric film and the polysilicon film of the plate is in turn included in sequence.

본 발명을 첨부된 제2a도 내지 제2e도를 참조하여 설명하면 다음과 같다.The present invention will be described with reference to FIGS. 2A through 2E as follows.

먼저 제2a도와 같이 실리콘기판(1)위에 워드라인(2)을 형성하고 워드라인(2)을 마스크로 이용하여 노출된 반도체 기판(1)에 이온주입으로 소오스 및 드레인(도면에는 도시되지 않음)을 형성한다.First, as shown in FIG. 2A, a word line 2 is formed on the silicon substrate 1, and a source and a drain are formed by ion implantation into the exposed semiconductor substrate 1 using the word line 2 as a mask (not shown). To form.

이어서 제1산화막(3)과 질화막(4)을 차례로 증착한 다음 사진 및 식각공정을 거쳐 워드라인(2)사이의 소오스영역에 콘택트 홀(Contact hole)을 형성한다.Subsequently, the first oxide film 3 and the nitride film 4 are sequentially deposited, and then contact holes are formed in the source region between the word lines 2 through the photolithography and etching processes.

그리고 제2b도와 같이 상기 콘택트 홀이 충분히 메꾸어지도록 상기 질화막(4)표면으로부터 소정높이까지 제1폴리실리콘막(5)을 증착하고, 이어 제2산화막(6)과 제2폴리실리콘막(7)을 차례로 증착한다.Then, as shown in FIG. 2B, the first polysilicon film 5 is deposited from the surface of the nitride film 4 to a predetermined height so that the contact hole is sufficiently filled. Then, the second oxide film 6 and the second polysilicon film 7 are deposited. In order to deposit.

이어 제2c도와 같이 상기 제2폴리실리콘막(7)상에 사진 및 식각공정을 실시하여 각 워드라인(2)의 상측 부분을 제외하곤 제2폴리실리콘막(7) 및 제2산화막(6)의 잔여부분을 제거함으로써 각 워드라인(2)상측에 소정폭의 산화막/폴리실리콘막 블럭을 형성한 다음 전체적으로 소정 두께의 제3폴리실리콘막(8)을 증착한다.Subsequently, as shown in FIG. 2C, the second polysilicon layer 7 and the second oxide layer 6 may be photographed and etched on the second polysilicon layer 7 except for the upper portion of each word line 2. By removing the remaining portion of the word line 2, an oxide film / polysilicon film block having a predetermined width is formed on each word line 2, and then a third polysilicon film 8 having a predetermined thickness is deposited.

이어 제2d도와 같이 RIE 공정을 실시하여 각 워드라인(2)의 상측에 위치한 각 산화막/폴리실리콘막 블럭에 측벽 폴리실리콘막(8a)을 형성한다.Subsequently, as shown in FIG. 2D, the RIE process is performed to form the sidewall polysilicon film 8a on each oxide film / polysilicon film block located above each word line 2.

그리고 산화막 에쳔트에 디핑하여 상기 산화막/폴리실리콘막 블럭중 제2산화막(6)을 선택적으로 제거함으로써 각 워드라인(2)상측에 중공 형태의 스토리지 노드 폴리실리콘막을 완성한다.The second oxide film 6 is selectively removed from the oxide film / polysilicon film block by dipping in an oxide film to form a hollow storage node polysilicon film on each word line 2.

마지막으로 제2e도와 같이 스토리지 노드 폴리실리콘막의 표면에 커패시터 유전체막(9)과 플레이트 폴리실리콘막(10)을 차례로 증착한다.Finally, as shown in FIG. 2E, the capacitor dielectric layer 9 and the plate polysilicon layer 10 are sequentially deposited on the surface of the storage node polysilicon layer.

이때 커패시터 유전체막(9)과 플레이트 폴리실리콘막(10)은 상기 중공 표면에도 증착하며 특히 플레이트 폴리실리콘막(10)은 상기 중공을 충분히 메꾸도록 증착한다.At this time, the capacitor dielectric film 9 and the plate polysilicon film 10 are also deposited on the hollow surface, and in particular, the plate polysilicon film 10 is deposited to sufficiently fill the hollow.

이와 같이 제조되는 본 발명의 디램 셀 구조는 소오스 및 드레인영역과 워드라인(2)이 형성된 반도체 기판(1)과, 상기 반도체 기판(1)상에 형성되고 소오스 영역에 콘택홀을 갖는 절연막과, 상기 소오스 영역에 연결되고 이웃한 워드라인상의 상기 절연막 위에 형성되는 제1폴리실리콘(5)과, 상기 제1폴리실리콘(5)양측 및 콘택홀 양 주변상부에 연결되는 기둥모양의 제3폴리실리콘(8a)과, 상기 콘택홀을 중심으로 양측 제3폴리실리콘(8a)상에 걸쳐 제1폴리실리콘(5)과 평행하게 각각 형성되는 제2폴리실리콘(7)과, 상기 제1, 제2, 제3폴리실리콘(5,8a,7)표면에 형성되는 유전체막(9)과 플레이트 폴리실리콘(10)을 포함하여 구성됨을 특징으로 하는 디램 셀의 구조로 이루어진다.The DRAM cell structure of the present invention manufactured as described above includes a semiconductor substrate 1 having a source and drain region and a word line 2 formed thereon, an insulating film formed on the semiconductor substrate 1 and having contact holes in the source region; First polysilicon (5) connected to the source region and formed on the insulating film on a neighboring word line, and columnar third polysilicon connected to both sides of the first polysilicon (5) and to upper peripheral portions of contact holes; (8a), second polysilicon (7) formed on both sides of the third polysilicon (8a) on both sides of the contact hole in parallel with the first polysilicon (5), and the first and second And a dielectric film 9 and a plate polysilicon 10 formed on the surface of the third polysilicon 5, 8a, and 7.

이상과 같이 본 발명에 따르면 다음과 같다According to the present invention as described above is as follows.

첫째, 종래 공정보다 디램 셀의 커패시턴스를 증대시킬 수 있게 된다.First, it is possible to increase the capacitance of the DRAM cell than the conventional process.

둘째, 스토리지 노드 형성 이전에 미리 산화막과 질화막을 이용하여 표면을 평탄화시킨 후 스토리지 노드 형성공정을 진행함으로서 공정중 스텝 커버리지 불량의 우려를 방지할 수 있게 된다.Second, before the storage node is formed, the surface is planarized using an oxide film and a nitride film in advance, and the storage node forming process is performed to prevent the possibility of poor step coverage during the process.

Claims (2)

워드라인 형성이후 진행되는 디램 셀 제조공정에 있어서, 제1산화막과 질화막을 차례로 증착하고 워드라인 사이에 콘택홀을 형성하는 스텝, 상기 콘택트 홀의 기저부위부터 상기 질화막상의 소정높이까지 제1폴리실리콘막을 증착한 후 제2산화막과 제2폴리실리콘막을 차례로 형성하는 스텝과, 각 워드라인 상측에 소정폭의 제2산화막/제2폴리실리콘막 블럭을 형성하는 스텝, 상기 블럭측면에 측벽 폴리실리콘막을 형성하는 스텝, 상기 블럭중 제2산화막을 제거하여 중공 쌍 형태의 스토리지노드 폴리실리콘막을 완성하는 스텝, 상기 스토리지 노드 폴리실리콘막 표면에 커패시터 유전체막을 증착하고 그 위에 상기 중공이 충분히 메꿔지도록 플레이트 폴리실리콘막을 증착하는 스텝을 포함하여 이루어짐을 특징으로 하는 디램 셀 제조방법.In the DRAM cell fabrication process which is performed after the word line formation, the step of depositing the first oxide film and the nitride film sequentially and forming a contact hole between the word lines, and forming the first polysilicon film from the base of the contact hole to a predetermined height on the nitride film Forming a second oxide film and a second polysilicon film sequentially after the deposition; forming a second oxide film / second polysilicon film block having a predetermined width above each word line; and forming a sidewall polysilicon film on the side of the block. Removing the second oxide film from the block to complete the storage node polysilicon film in the form of a hollow pair; depositing a capacitor dielectric film on the surface of the storage node polysilicon film; and filling the plate polysilicon film so that the hollow is sufficiently filled thereon. DRAM cell manufacturing method comprising the step of depositing. 소오스 및 드레인영역과 워드라인이 형성된 반도체 기판과, 상기 반도체 기판상에 형성되고 소오스 영역에 콘택홀을 갖는 절연막과, 상기 소오스 영역에 연결되고 이웃한 워드라인상의 상기 절연막 위에 형성되는 제1폴리실리콘과, 상기 제1폴리실리콘 양측 및 콘택홀 양 주변상부에 연결되는 기둥모양의 제3폴리실리콘과, 상기 콘택홀을 중심으로 양측 제3폴리실리콘상에 걸쳐 제1폴리실리콘과 평행하게 각각 형성되는 제2폴리실리콘과, 상기 제1,제2,제3폴리실리콘 표면에 형성되는 유전체막과 플레이트 폴리실리콘을 포함하여 구성됨을 특징으로 하는 디램 셀의 구조.A semiconductor substrate having a source and drain region and a word line formed thereon, an insulating film formed on the semiconductor substrate and having a contact hole in the source region, and a first polysilicon formed on the insulating film connected to the source region and adjacent to the word line; And pillar-shaped third polysilicon connected to both upper sides of the first polysilicon and upper contact holes, and parallel to the first polysilicon on both sides of the third polysilicon around the contact hole. A structure of a DRAM cell comprising a second polysilicon, a dielectric film formed on a surface of the first, second and third polysilicon and a plate polysilicon.
KR1019910011918A 1991-07-12 1991-07-12 Method of fabricating a dram cell and structure thereof KR940004600B1 (en)

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