KR940004273B1 - Different type vertical ccd structure - Google Patents

Different type vertical ccd structure Download PDF

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Publication number
KR940004273B1
KR940004273B1 KR1019910002373A KR910002373A KR940004273B1 KR 940004273 B1 KR940004273 B1 KR 940004273B1 KR 1019910002373 A KR1019910002373 A KR 1019910002373A KR 910002373 A KR910002373 A KR 910002373A KR 940004273 B1 KR940004273 B1 KR 940004273B1
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vccd
vertical
photodiode
photodetectors
gate electrodes
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KR1019910002373A
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KR920017280A (en
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이서규
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금성일렉트론 주식회사
문정환
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Priority to KR1019910002373A priority Critical patent/KR940004273B1/en
Priority to DE4203825A priority patent/DE4203825C2/en
Priority to JP4025131A priority patent/JP2592193B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/73—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors using interline transfer [IT]

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A CCD image sensor of an interlaced scanning type comprises: a plurality of uniformly spaced photodetectors which accumulate signal charges in response to incident light and are arranged in series in vertical; a plurality of VCCD regions arranged between the vertical lines of the photodetectors; a plurality of channel stop regions for electrically isolating a plurality of photodetectors from one another; a plurality of gate electrodes formed on the VCCD regions, each of gate electrodes being connected simultaneously to the transfer gate electrodes of a plurality of photodetector pairs; and a plurality of barrier layers which correspond to a part of each VCCD region, formed in order to form a desired potential threshold.

Description

이상 수직 CCD 구조Ideal vertical CCD structure

제1도는 종래의 VCCD 평면 구조도.1 is a conventional VCCD planar structure diagram.

제2도는 제1도에서 A-A의 포텐셜 상태도.2 is a potential state diagram of A-A in FIG.

제3도는 본 발명의 VCCD 평면 구조도.3 is a VCCD planar structure diagram of the present invention.

제4도는 제3도에서 채널 스톱영역 구조도.4 is a structural diagram of a channel stop region in FIG. 3;

제5도는 제3도에서 B-B의 포텐셜 상태도.5 is a potential state diagram of B-B in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 포토다이오드 2 : 채널스톱1: photodiode 2: channel stop

3, 4 : 폴리 5 : 배리어3, 4: poly 5: barrier

본 발명은 CCD에 관한 것으로, 특히 인터레이싱(Intor-Lacing) 방식에 적당하도록 한 수직 구동방식의 이상 수직(Two-Phase Vertical) CCD 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to CCDs, and more particularly, to a two-phase vertical CCD structure of a vertical driving method suitable for an interlacing method.

종래의 수직 CCD는 4상 클럭킹으로써 제1도에 도시된 바와 같이 이중폴리(3,4)를 사용하였고, 폴리중 하나의 폴리게이트로 포토다이오드(1) 부분의 신호 전하를 VCCD 포켓에 싣는 방식이다.Conventional vertical CCD uses bi-poly (3, 4) as shown in Figure 1 as a four-phase clocking, the method of loading the signal charge of the photodiode (1) portion in the VCCD pocket with one poly gate of the poly to be.

즉, VCCD 부분의 폴리게이트(3,4)중 하나의 폴리게이트를 트라이 레벨 크럭킹을 하여 포토다이오드(1)의 신호 전하를 VCCD 포켓에 담고, 제2도와 같이 4상 클럭(VФ1-VФ2)을 구동시켜 클럭(VФ1)이 하이일 경우 클럭(VФ1-VФ2)을 로우로 하여 포텐셜 장벽을 만들어 줌으로써 하나의 신호전하 포켓을 만들 수 있다.That is, one of the polygates 3 and 4 of the VCCD portion is tri-level clocked to store the signal charge of the photodiode 1 in the VCCD pocket, and the four-phase clock (VФ 1 -VФ) as shown in FIG. If the clock VФ 1 is high by driving 2 ), one signal charge pocket can be made by creating a potential barrier by setting the clocks VФ 1 -VФ 2 low.

따라서 이러한 신호 전하를 이동시킬 경우는 4개의 클럭에 게이트 바이어스를 변화시켜 신호전하를 이동시켜 리드-아웃한다.Therefore, when the signal charge is moved, the gate charge is changed to four clocks, and the signal charge is moved to read out.

미설명 부호 2는 채널스톱이다.Reference numeral 2 is a channel stop.

그러나 이와 같은 종래의 기술구성에 있어서는 VCCD 부분의 구동 클럭킹 수가 4개가 되어 구동방식의 복잡하고 구동단자가 많으며 신호가 VCCD 포켓에 실려도 다시 전하를 혼합시키는 구동방식이 필요하게 되어 복잡함 단점이 있었다.However, in the conventional technical configuration, the driving clocking number of the VCCD portion is four, so the driving method is complicated, and there are many driving terminals, and a driving method for mixing the charges even when a signal is carried in the VCCD pocket is required.

본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로서 VCCD 구동클럭킹을 2상으로 할 수 있도록 하는데 그 목적이 있다.The present invention has been made in order to solve such a problem, and its object is to enable VCCD driving clocking to be in two phases.

이와 같은 목적을 달성하기 위한 본 발명을 첨부된 도면을 참조하여 설명하면 다음과 같다.When explaining the present invention for achieving the above object with reference to the accompanying drawings as follows.

제3도는 본 발명의 VCCD 평면도이고, 제4도는 제3도의 채널스톱영역 구조도이고, 제5도는 제3도에서 B-B-'선상의 포텐셜 단면도로써, 본 발명의 VCCD는 빛의 신호를 전기적인 신호로 변환하는 복수개의 포토다이오드(1,1')가 수직수평방향으로 일정간격을 갖고 매트릭스(Matrix) 형태로 배열되고, 포토다이오드와 포토다이오드 사이의 수직방향으로 수직전하전송 채널이 형성되고, 각 포토다이오드 주위에는 전기적인 신호를 격리시키는 채널스톱(channel stop)영역이 형성되고, 상기 수직 전하전송 채널상에는 수직방향으로 2개의 제1, 제2게이트(3,4)가 오버랩(over lap)되어 반복적으로 형성되어 구성된다.3 is a plan view of the VCCD of the present invention, FIG. 4 is a structural diagram of the channel stop region of FIG. 3, and FIG. A plurality of photodiodes (1,1 ') to be converted into a matrix are arranged in a matrix form at regular intervals in the vertical and horizontal directions, and a vertical charge transfer channel is formed in the vertical direction between the photodiode and the photodiode. A channel stop region is formed around the photodiode to isolate electrical signals, and two first and second gates 3 and 4 overlap each other in the vertical direction on the vertical charge transfer channel. It is formed and configured repeatedly.

여기서, 제2게이트(47)는 포토다이오드(1,1') 영역에서 수직전하전송 채널로 광전하를 전송하기 위해 채널스톱영역을 지나 이웃한 포토다이오드와 중첩되도록 형성되며, 제1, 제2게이트의 일측 하부의 수직전하전송 채널에는 베리어(5)층이 형성된다.Here, the second gate 47 is formed so as to overlap with the neighboring photodiode through the channel stop region in order to transfer the photocharge from the photodiode (1, 1 ') region to the vertical charge transfer channel. A barrier 5 layer is formed in the vertical charge transfer channel under one side of the gate.

이와 같은 구조를 갖는 본 발명의 이상수직 CCD의 제조방법은 다음과 같다.The manufacturing method of the ideal vertical CCD of this invention which has such a structure is as follows.

즉, p형 실리콘기판 위에 액티브영역을 정의한 후(나머지 부분 필드부분)에 필드산화막을 선택적으로 옥시데이션(Oxidation)한다.That is, after defining an active region on the p-type silicon substrate (the remaining partial field portion), the field oxide film is selectively oxidized.

제4도와 같이 액티브영역중 채널스톱 형성영역만 노출되도록 마스크 작업을 하여 p형 이온주입을 실시하여 채널스톱(2) 영역을 형성한다.As shown in FIG. 4, a p-type ion implantation is performed to mask only the channel stop formation region in the active region, thereby forming the channel stop 2 region.

그리고 다시 포토다이오드 형성영역과 VCCD 채널 형성영역이 노출되도록 마스크 작업을 하여 노출된 실리콘기판에 n형 이온주입을 실시하여 VCCD 채널상에 일정간격으로 p형 이온주입하여 베리어(6)층을 형성한다.Then, a mask operation is performed to expose the photodiode forming region and the VCCD channel forming region, and n-type ion implantation is performed on the exposed silicon substrate, and p-type ion implantation is performed on the VCCD channel at a predetermined interval to form a barrier (6) layer. .

포토다이오드 영역과 VCCD 채널영역을 형성한 다음 전면에 제1게이트 절연막을 형성한 뒤 폴리실리콘을 증착하고 식각하여 VCCD 채널영역상에 일정한 간격으로 복수개의 제1게이트를 형성한다.After forming the photodiode region and the VCCD channel region, a first gate insulating layer is formed on the entire surface, polysilicon is deposited and etched to form a plurality of first gates on the VCCD channel region at regular intervals.

그리고 전면에 제2게이트 절연막을 증착한 다음, 폴리실리콘을 증착하고 식각하여 제1게이트 사이에 복수개의 제2게이트를 형성한다.The second gate insulating layer is deposited on the entire surface, and then polysilicon is deposited and etched to form a plurality of second gates between the first gates.

이때 제2게이트는 제1게이트와 모서리 부분에서 오버랩되고 이웃한 포토다이오드에 걸쳐지도록 패터닝되며 제1, 제2게이트(3,4)는 일정간격으로 베리어층을 규칙적으로 게이트 전극 일측에 오도록 형성한다.At this time, the second gate is overlapped at the corner portion of the first gate and is patterned to span the neighboring photodiode, and the first and second gates 3 and 4 are formed so that the barrier layer regularly comes to one side of the gate electrode at a predetermined interval. .

이와 같이 구성되고 제조된 본 발명의 이상수직 VCCD의 동작은 다음과 같다.The operation of the ideal vertical VCCD of the present invention constructed and manufactured as described above is as follows.

즉, 제5도에서와 같이 제2게이트(4)에 클럭(VФ2)이 인가되면, 해당부위의 VCCD 채널의 포텐셜이 아래로 내려가게 되어 포텐셜 포켓이 생기게 되고 여기에 포토다이오드(1)의 신호전하가 이동되어 모이게 된다.That is, as shown in FIG. 5, when the clock VФ 2 is applied to the second gate 4, the potential of the VCCD channel of the corresponding portion is lowered to form a potential pocket, whereby the photodiode 1 of the photodiode 1 Signal charges move and gather.

그리고 제1, 제2게이트(3,4)에 클럭신호(VФ1,VФ2)을 변화시켜 이동하게 되면, 전하를 일방향으로 이동하게 된다.When the clock signals VФ 1 and VФ 2 are moved to the first and second gates 3 and 4, charges move in one direction.

제5도에서 동일 게이트 하여서 포텐셜이 다른 이유는 그 부분에 베리어(5)층이 형성되었기 때문이다.The reason why the potential is different in the same gate in FIG. 5 is that the barrier 5 layer is formed in the portion.

Claims (1)

수직, 수평방향으로 일정간격으로 갖는 매트릭스 형태로 배열되어 빛의 신호를 전기적인 신호로 변환하여 신호전하를 생성하는 복수개의 포토다이오드와, 상기 포토다이오드들 사이의 수직방향으로 형성되어 신호전하를 전송하기 위한 복수개의 수직전하전송 채널과, 상기 각 포토다이오드 주위에 전기적인 신호를 격리시키기 위한 채널스톱영역과, 상기 수직전하전송 채널상에 반복적으로 형성되는 복수개의 제1, 제2게이트와, 수직전하전송 채널상에 수직방향으로 제1, 제2게이트의 일측 하부에 형성되는 베리어층을 포함하여 구성됨을 특징으로 하는 이상수직 CCD 구조.A plurality of photodiodes arranged in a matrix form at regular intervals in the vertical and horizontal directions to convert a signal of light into an electrical signal to generate signal charges, and formed in a vertical direction between the photodiodes to transmit signal charges A plurality of vertical charge transfer channels, a channel stop region for isolating electrical signals around each photodiode, a plurality of first and second gates repeatedly formed on the vertical charge transfer channels, and And a barrier layer formed below one side of the first and second gates in a vertical direction on the charge transfer channel.
KR1019910002373A 1991-02-12 1991-02-12 Different type vertical ccd structure KR940004273B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019910002373A KR940004273B1 (en) 1991-02-12 1991-02-12 Different type vertical ccd structure
DE4203825A DE4203825C2 (en) 1991-02-12 1992-02-10 CCD image sensor
JP4025131A JP2592193B2 (en) 1991-02-12 1992-02-12 CCD image element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910002373A KR940004273B1 (en) 1991-02-12 1991-02-12 Different type vertical ccd structure

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KR920017280A KR920017280A (en) 1992-09-26
KR940004273B1 true KR940004273B1 (en) 1994-05-19

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DE4329838B4 (en) * 1993-09-03 2005-09-22 Hynix Semiconductor Inc., Ichon Solid-state image sensor
DE4329837B4 (en) * 1993-09-03 2005-12-29 Magnachip Semiconductor, Ltd. Method of manufacturing a silicon semiconductor device

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JPS55163960A (en) * 1979-06-08 1980-12-20 Nec Corp Electric charge transfer pickup unit
JPS58200574A (en) * 1982-05-18 1983-11-22 Matsushita Electric Ind Co Ltd Solid state image pickup device
JPS6156583A (en) * 1984-08-27 1986-03-22 Sharp Corp Solid-state image pickup device
JPS61114663A (en) * 1984-11-09 1986-06-02 Sharp Corp Solid-state image pickup device
JP2508668B2 (en) * 1986-11-10 1996-06-19 ソニー株式会社 Charge transfer device
JPH01241161A (en) * 1988-03-23 1989-09-26 Hitachi Ltd Solid-state image sensing device

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KR920017280A (en) 1992-09-26
JP2592193B2 (en) 1997-03-19
DE4203825A1 (en) 1992-08-13
JPH07170459A (en) 1995-07-04

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