KR100259064B1 - Method of manufacturing ccd image device - Google Patents
Method of manufacturing ccd image device Download PDFInfo
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- KR100259064B1 KR100259064B1 KR1019920010138A KR920010138A KR100259064B1 KR 100259064 B1 KR100259064 B1 KR 100259064B1 KR 1019920010138 A KR1019920010138 A KR 1019920010138A KR 920010138 A KR920010138 A KR 920010138A KR 100259064 B1 KR100259064 B1 KR 100259064B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
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Abstract
Description
제 1 도는 종래 HCCD 영역의 구조 평면도1 is a structural plan view of a conventional HCCD region
제 2 도는 종래 HCCD 영역의 구조 단면도2 is a structural cross-sectional view of a conventional HCCD region
제 3 도는 일반적인 2페이즈 클럭킹에 의한 포텐셜 프로파일Figure 3 shows the potential profile by normal two-phase clocking.
제 4 도는 본 발명 HCCD 영역의 구조 평면도4 is a structural plan view of the HCCD region of the present invention.
제 5 도는 본 발명 HCCD 영역의 구조 단면도5 is a structural cross-sectional view of the HCCD region of the present invention.
제 6 도는 본 발명에 따른 1실시예의 HCCD 영역 공정 단면도6 is a cross-sectional view of an HCCD region in one embodiment according to the present invention.
제 7 도는 본 발명에 따른 2실시예의 HCCD 영역의 공정 단면도7 is a process sectional view of the HCCD region of the second embodiment according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형 웰 2 : 전하전송영역1: P type well 2: charge transfer region
3 : 제 1 게이트전극 4 : 제 2 게이트전극3: first gate electrode 4: second gate electrode
5, 5a : 베리어층 6 : 제 3 게이트전극5, 5a: barrier layer 6: third gate electrode
본 발명은 CCD(Charge Coupled Device) 영상소자에 관한 것으로 특히, 게이트전극 하부의 불순물 농도를 조절하여 투 페이스 클럭킹(Two Phase Clocking)구조를 갖는 수평 전하전송영역(Horizontal CCD)에 관한 것이다.The present invention relates to a charge coupled device (CCD) imaging device, and more particularly, to a horizontal charge transfer region (Horizontal CCD) having a two phase clocking structure by controlling an impurity concentration under the gate electrode.
일반적으로 CCD 영상소자는 실리콘과 같은 반도체 기판에 빛의 신호를 전기적인 신호로 변환하는 복수개의 포토다이오드 등을 메트릭스 형태로 배열하여 영상신호 전하를 생성하는 복수개의 광전변환소자와, 광전변환소자 사이에 규칙적으로 배열되어 광전변환소자에 의해 생성된 영상신호 전하를 수직방향으로 전송하는 수직 전하전송영역(Vertical CCD)과, 수직 전하전송영역(VCCD)에 의해 전송된 영상신호 전하를 수평방향으로 전송하기 위해 수직 전하전송영역의 출력측에 형성된 수평전하전송영역(HCCD)과, 수평 전하전송영역(HCCD)의 출력단에서 전송된 영상신호 전하를 센싱하는 센싱엠프가 구성되어 이루어진 고체 촬상 소자이다.In general, a CCD image device includes a plurality of photodiodes for generating an image signal charge by arranging a plurality of photodiodes for converting a light signal into an electrical signal on a semiconductor substrate such as silicon in an matrix form, and a photoelectric conversion device. The vertical charge transfer region (Vertical CCD) and the vertical charge transfer region (VCCD) transfer the image signal charges generated by the photoelectric conversion element in a vertical direction and are arranged regularly in the horizontal direction. To this end, a horizontal charge transfer region HCCD formed on the output side of the vertical charge transfer region and a sensing amplifier for sensing the image signal charge transferred from the output terminal of the horizontal charge transfer region HCCD are configured.
이와 같이 구성된 종래의 CCD 영상소자중 수평 전하전송영역(HCCD)을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a horizontal charge transfer region HCCD among the conventional CCD image elements configured as described above is as follows.
제 1 도는 종래의 수평 전하전송영역의 구조 평면도이고, 제 2 도는 제 1 도의 A-A'선상의 구조 단면도를 나타낸 것으로서, 제 1 도는 전하전송영역(Buried CCD)(2)상측에 전하를 전송하기 위한 클럭신호를 인가하는 폴리실리콘으로 된 제 1 게이트전극(3)과 제 2 게이트전극(4)들이 일정간격을 유지하며 번갈아 형성되어 있는 것을 나타내고 있다.1 is a structural plan view of a conventional horizontal charge transfer region, and FIG. 2 is a structural cross-sectional view taken along the line A-A 'of FIG. 1, and FIG. 1 transfers charges above the buried CCD region 2. The first gate electrode 3 and the second gate electrode 4 made of polysilicon to which the clock signal is applied are alternately formed at regular intervals.
제 2 도는 n형 실리콘기판(도시되지 않음)에 P형 웰(Well)(1)을 형성하고, P형 웰(1)내에 n형 이온주입으로 전하전송영역(2)을 형성한다.2 shows a P type well 1 in an n type silicon substrate (not shown), and a charge transfer region 2 is formed by n type ion implantation in the P type well 1.
그리고 그 위에 절연막(7)을 형성하고, 폴리실리콘을 증착하며 포토에치 공정으로 제 1 게이트전극(3)을 패터닝한 뒤 제 1 게이트전극(3)을 마스크로 하여 전하전송영역(2)에 저농도 n형 영역을 만들어 베리어층(5)을 형성하고 제 1 게이트전극(3) 사이사이에 제 1 게이트전극(3)과 격리되어 제 2 게이트전극(4)이 형성된 구조이다.Then, an insulating film 7 is formed thereon, polysilicon is deposited, the first gate electrode 3 is patterned by a photoetch process, and the first gate electrode 3 is used as a mask in the charge transfer region 2. The barrier layer 5 is formed by forming a low concentration n-type region, and the second gate electrode 4 is formed by being separated from the first gate electrode 3 between the first gate electrodes 3.
여기서 제 1 게이트전극(3)과 제 2 게이트전극(4)을 한쌍으로 하여 제 1 클럭신호(H 1)와 제 2 클럭신호(H 2)가 번갈아 인가되어 있다.In this case, the first clock signal H is formed by pairing the first gate electrode 3 and the second gate electrode 4. 1 ) and the second clock signal H 2 ) are alternately applied.
이와 같이 구성된 수평 전하전송영역(HCCD)의 투페이스 클럭킹(Two Phase Clocking)에 의한 포텐셜 및 전하이동을 설명을 제 3 도에 나타내었다.The potential and charge transfer due to two phase clocking of the horizontal charge transfer region HCCD configured as described above are illustrated in FIG. 3.
즉, 제 1 클럭신호(H 1)와 제 2 클럭신호(H 2)에 의해 포텐셜이 변함에 따라 전하가 수평방향으로 이동된다.That is, the first clock signal H 1 ) and the second clock signal H The charge is moved in the horizontal direction as the potential is changed by 2 ).
이때 제 1 게이트전극(3)과 제 2 게이트전극(4)에 같은 바이어스가 걸려도 제 2 게이트전극(4) 하측에 베리어층(5)이 형성되어 있으므로 제 1 게이트전극(3)과 제 2 게이트전극(4)에 의해 전하전송영역은 포텐셜 단차를 갖는다.At this time, even if the first gate electrode 3 and the second gate electrode 4 are subjected to the same bias, the barrier layer 5 is formed under the second gate electrode 4, so that the first gate electrode 3 and the second gate are formed. By the electrode 4, the charge transfer region has a potential step.
그러나 이와 같은 종래의 CCD 영상소자의 수평 전하전송영역(HCCD)은 전하전송영역(2)에 포텐셜(Potential)단차를 갖기 위해 제 2 게이트전극(4) 하측에 베리어 임프런트(barrier Implant)를 실시한다.However, the horizontal charge transfer region HCCD of the conventional CCD imaging device performs a barrier implant below the second gate electrode 4 so as to have a potential step in the charge transfer region 2. do.
그런데 게이트전극을 두 개로 할 경우 베리어층 및 전극의 길이 조절을 서브-마이크로(Sub-micro)이하로 하기가 어렵기 때문에 고속 동작에 한계가 있고 해상도가 저하되는 문제점이 있다.However, when two gate electrodes are used, it is difficult to control the length of the barrier layer and the electrode to be less than the sub-micro.
본 발명은 이와 같은 문제점을 개선하기 위해 안출한 것으로서, 전하전송영역 형성시의 불순물을 조절하여 포텐셜 단차를 갖도록 하여 전하 전송 효율을 향상시키도록 한 CCD 영상소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a CCD image device in which charge impurity is improved by controlling impurities in forming a charge transfer region to have a potential step.
이와 같은 목적을 달성하기 위한 본 발명을 첨부된 도면을 참조하여 설명하면 다음과 같다.When explaining the present invention for achieving the above object with reference to the accompanying drawings as follows.
제 4 도는 본 발명의 수평 전하전송영역의 구조 평면도로써, 전하전송영역(2) 상측에 클럭신호를 인가하기 위한 게이트전극인 제 1 게이트전극 및 제 2 게이트전극, 제 3 게이트 전극(3, 4, 6)들이 형성되어 투페이즈 클럭킹을 동작됨을 나타내고 있다.4 is a plan view of a horizontal charge transfer region according to the present invention, in which a first gate electrode, a second gate electrode, and a third gate electrode 3, 4, which are gate electrodes for applying a clock signal on the charge transfer region 2, are shown in FIG. , 6) are formed to indicate that two-phase clocking is operated.
제 5 도는 제 4 도의 B-B'선상의 단면도로서, n형 실리콘기판(도시되지 않음)에 P형 웰(1)이 형성되고, P형 웰(1)내에 소정간격으로 저농도층에 형성된 n형 전하전송영역(2)이 형성되고, 전하전송영역(2)위에 절연막(7)이 형성되고, 절연막(7) 위에 제 1, 제 2, 제 3 게이트전극(3, 4, 6)들이 형성된다.5 is a cross-sectional view taken along the line B-B 'of FIG. 4, in which a P-type well 1 is formed on an n-type silicon substrate (not shown), and n is formed in a low concentration layer at a predetermined interval in the P-type well 1; A type charge transfer region 2 is formed, an insulating film 7 is formed on the charge transfer region 2, and first, second, and third gate electrodes 3, 4, 6 are formed on the insulating film 7. do.
여기서 제 3 게이트전극은 전하전송영역(2)중 저농도층의 상부측위에 형성되어 제 1 게이트전극(3)과는 연결되고, 제 2 게이트전극(4)과는 격리되어 있다.Here, the third gate electrode is formed on the upper side of the low concentration layer in the charge transfer region 2, is connected to the first gate electrode 3, and is isolated from the second gate electrode 4.
그리고, 제 1 게이트전극(3)과 제 2 게이트전극(4)은 격리되어 있으므로 제 1 게이트전극(3)과 제 2 게이트전극(4)을 한쌍으로 하여 제 1, 제 2 클럭신호(H 1, H 2)가 번갈아 인가된 구조이다.Since the first gate electrode 3 and the second gate electrode 4 are separated from each other, the first and second clock signals H may be paired with the first gate electrode 3 and the second gate electrode 4. 1 , H 2 ) is alternately applied structure.
상기와 같이 구성된 본 발명의 수평 전하전송영역(HCCD)의 공정을 제 6 도 및 제 7 도에 나타내었다.The process of the horizontal charge transfer region (HCCD) of the present invention configured as described above is shown in FIG. 6 and FIG.
즉, 제 6 도는 본 발명에 따른 제 1 실시예의 수평 전하전송영역(HCCD)의 공정단면도로써, 제 6 도(a)와 n형 실리콘기판에 P형 웰(1)을 형성하고 전면에 저농도 n형 이온주입하여 베리어층(5a)을 형성한다.6 is a process cross-sectional view of the horizontal charge transfer region HCCD according to the first embodiment of the present invention, in which the P-type well 1 is formed on the n-type silicon substrate and in FIG. Type ion implantation forms the barrier layer 5a.
그리고 제 6 도(b)와 같이 폴리실리콘을 증착하고 포토에치 공정으로 패터닝하여 제 3 게이트전극(6)을 소정의 간격으로 형성한 다음, 제 6 도(c)와 같이 제 3 게이트전극(6)을 마스크로 하여 베리어층(5a)에 다시 n형 이온주입을 실시하여 제 3 게이트전극(6) 하측이 베리어층(5)이 되도록 전하전송영역(2)을 형성한다.As shown in FIG. 6 (b), polysilicon is deposited and patterned by a photoetch process to form third gate electrodes 6 at predetermined intervals, and then as shown in FIG. Using n) as a mask, n-type ion implantation is again performed on the barrier layer 5a to form the charge transfer region 2 such that the lower side of the third gate electrode 6 becomes the barrier layer 5.
그리고 제 6 도(d)와 같이 제 3 게이트전극(6)과 연결되도록 제 1 게이트전극(3)을 형성하고, 제 6 도(e)와 같이 제 3 게이트전극(6)과 제 1 게이트전극(3)사이에 제 1, 제 3 게이트전극(3, 6)과 격리되게 제 2 게이트전극(4)을 형성하여 수평전하전송영역을 제조한다.The first gate electrode 3 is formed to be connected to the third gate electrode 6 as shown in FIG. 6 (d), and the third gate electrode 6 and the first gate electrode as shown in FIG. 6 (e). A second charge electrode 4 is formed between (3) to be isolated from the first and third gate electrodes 3 and 6 to form a horizontal charge transfer region.
여기서 도면에는 도시하지 않았지만 제 1, 제 2, 제 3 게이트전극(3, 4, 6)과 전하전송영역(2)은 절연막으로 격리되어 있다.Although not shown in the drawing, the first, second and third gate electrodes 3, 4 and 6 and the charge transfer region 2 are separated by an insulating film.
한편 제 7 도는 본 발명에 따른 제 2 실시예의 수평 전하전송영역의 공정단면도로써, 제 7 도(a)와 같이 n형 실리콘기판에 P형 웰(1)을 형성하고, 그 위에 소정간격을 두고 제 3 게이트전극(6)을 형성한다.7 is a process cross-sectional view of a horizontal charge transfer region of a second embodiment according to the present invention, in which a P-type well 1 is formed on an n-type silicon substrate as shown in FIG. The third gate electrode 6 is formed.
그리고 제 7 도(b)와 같이 제 3 게이트전극(6)을 마스크로하여 n형 이온주입하고 어닐링하여 전하전송영역(2)을 형성한다.As shown in FIG. 7B, the n-type ion implanted and annealed using the third gate electrode 6 as a mask to form the charge transfer region 2.
그리고 제 7 도(c)와 같이 제 3 게이트전극(6)과 연결되게 제 1 게이트전극(3)을 형성하고 제 7 도(d)와 같이 제 2 게이트전극(4)을 제 1 게이트전극(3) 사이에 제 1, 제 2, 제 3 게이트전극(3, 4, 6)과 격리되게 형성하여 수평 전하전송영역을 형성한다.As shown in FIG. 7C, the first gate electrode 3 is formed to be connected to the third gate electrode 6, and as shown in FIG. 7D, the second gate electrode 4 is formed as the first gate electrode ( 3) a horizontal charge transfer region is formed by separating the first, second and third gate electrodes 3, 4, and 6 from each other.
이상에서 설명한 바와 같이 본 발명에 의한 CCD 영상소자의 수평 전하전송영역에 있어서는 제 3 게이트전극의 일측에 연결되는 제 1 게이트전극을 형성하고, 제 3 게이트전극 하부에만 베리어층을 형성함으로서 투 페이즈 클럭킹 인가시 제 1, 제 3 게이트전극에도 포텐셜 단차를 갖도록 함으로써 소자의 고속 동작 및 해상도를 향상시킬 수 있는 효과가 있다.As described above, in the horizontal charge transfer region of the CCD image device according to the present invention, the first gate electrode connected to one side of the third gate electrode is formed, and the barrier layer is formed only under the third gate electrode, thereby making two-phase clocking. When applied, the first and third gate electrodes also have potential steps to improve the high-speed operation and resolution of the device.
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| KR1019920010138A KR100259064B1 (en) | 1992-06-11 | 1992-06-11 | Method of manufacturing ccd image device |
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| KR (1) | KR100259064B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541712B1 (en) * | 1996-01-18 | 2006-06-13 | 매그나칩 반도체 유한회사 | Linear CCD Imaging Device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100377105B1 (en) * | 2001-05-10 | 2003-03-19 | 에스케이 텔레콤주식회사 | Sender number edit method of call back number |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296275A (en) * | 1987-05-27 | 1988-12-02 | Sony Corp | Manufacture of charge transfer device |
-
1992
- 1992-06-11 KR KR1019920010138A patent/KR100259064B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296275A (en) * | 1987-05-27 | 1988-12-02 | Sony Corp | Manufacture of charge transfer device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541712B1 (en) * | 1996-01-18 | 2006-06-13 | 매그나칩 반도체 유한회사 | Linear CCD Imaging Device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940001431A (en) | 1994-01-11 |
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