KR100262006B1 - Solid-state image sensor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A solid-state image sensor and a method for manufacturing the same are provided to prevent the counter-doping of PD(photo diode) and VCCD(vertical charge coupled device) to minimize point defect and suppress dark current and white defect by separating an N type substrate into upper/lower substrates and using PD and VCCD in the upper substrate. CONSTITUTION: An N type substrate is separated into a lower N type substrate(N1) and an upper N type substrate(N2) by a first P type well(1PW). A plurality of second P type wells(2PW) are formed with constant interval on the upper N type substrate(N2), and N type photo diodes(PDN) are formed between the second P type wells(2PW). That is, the photo diodes are areas in which N type impurities are distributed with high density and the substrate(N2) is an area in which the impurities are distributed with low density. Channel stop layers(CST) are formed near the photo diodes(PDN) and a P type impurity layer(PDP) is formed on the photo diode. The resultant structure is covered with a first insulating film(32), on which first/second transfer gates(33,35) are formed. A second insulating film(37) is covered with a shading layer(38).

Description

Solid state imaging device and manufacturing method

The present invention relates to a solid-state image pickup device and a method of manufacturing the same. In particular, in the cross-sectional structure of the cell array portion, the first P-type well is deeply formed on the N-type substrate, and the substrate is separated into an upper portion and a lower portion. By using Photo Diode (hereinafter referred to as PD) and Vertical Charge Coupled Device (hereinafter referred to as VCCD), PD and VCCD are prevented from being counter-doped, and the concentration of PD and VCCD is also reduced. A solid state image pickup device for facilitating paragraph and spacing and a method of manufacturing the same.

1 shows a plan view of a general solid state image pickup device.

A solid state image pickup device is an apparatus for generating electrons by light, arranging charge-coupled devices in a directional manner, and detecting signal charges transmitted thereby. In other words, it is a device that transfers charges excited by light through a directional CCD array and then amplifies this signal to obtain a predetermined output signal. As such, the solid-state imaging device, which is an apparatus for converting an image signal into an electrical signal, includes a pixel array unit arranged as a unit cell consisting of a PD, which is a light receiving area, and a VCCD receiving signal charges generated and accumulated in the PD; A charge transfer region (Horizontal Charge Coupled Device, hereinafter referred to as HCCD) and a signal detector. The signal charges accumulated in the PD are sequentially transferred to the VCCD and the HCCD and output through the signal detection unit.

The operation of a general solid state image pickup device will be briefly described as follows. When the light focused through the microlens reaches the light receiving unit PD, the charge generated by the photoelectric effect accumulates in the potential well under the PD. The charge thus collected is transferred to the charge transfer path VCCD by the change of potential caused by the voltage across the transfer gate TG. The transmitted charge moves in sequence through the VCCD and then moves along a wider path called HCCD, which eventually collects on the floating gate. The charge collected in the floating gate is sensed by using the point that the potential of the floating gate changes up and down according to the amount of charge, and then is discharged to the drain.

2A to 2E are diagrams for explaining a solid state image pickup device according to the related art, and show a manufacturing process diagram for a partial cross-sectional structure of a pixel array unit.

Referring to FIG. 2A, a P-type impurity is formed by implanting and diffusing P-type impurities into an n-type semiconductor substrate (N-SUB) in the entire region in which the CCD operates, and then the portion where the VCCD is to be located. P-type impurities are implanted into and diffused into the second P-type wells 2PW.

Referring to FIG. 2B, an N-type impurity is injected and diffused into a portion where the PD is to be formed (a portion of the first P-type well 1PW where the second P-type well 2PW is not located) to form PD (PDN). next. The VCCD is formed by injecting and diffusing N-type impurities into the portion where the VCCD is to be formed (the portion of the first P-type well 1PW where the second P-type well 2PW is located).

Referring to FIG. 2C, a P-type impurity is implanted into and diffused into a predetermined portion of the substrate to form a channel stop region CST surrounding the PD (PDN). Thereafter, a first insulating film () covering the entire substrate is formed.

Referring to FIG. 2D, after the first polysilicon layer is deposited and etched on the first insulating layer 22 to form a first transfer gate 23, the first transfer gate 23 is oxidized to form a first transfer gate 23. An oxide insulating film 24 is formed. Subsequently, the second polysilicon layer is deposited and etched to form a second transfer gate 25 positioned on the first transfer gate 23, and then the second transfer gate 25 is oxidized to oxidize the second. The insulating film 26 is formed. Subsequently, a P-type impurity layer (PDP) is formed on the upper surface of the PD by injecting and diffusing the P-type impurity into the surface of the PD.

Referring to FIG. 2E, after forming the second insulating film 27 covering the exposed entire surface, a metal layer deposition and etching process is performed on the second insulating film 27 to cover portions except for PD (PDN). 28). Subsequently, an insulating material is deposited on the exposed entire surface of the substrate to form a protective film 29 that protects the substrate.

In the above-described conventional technique, the PD is formed by injecting P-type impurities into an N-type substrate to form a P-type well, and then injecting N-type impurities. That is, counter-doping is repeatedly performed to form PD. However, counter doping of such impurities creates a large amount of point defects. In addition, when repeated counter-doping is performed, the distribution of impurities is uneven due to the temperature of a subsequent thermal process such as diffusion work. Therefore, in the related art, even if the same amount of impurity is injected, the concentration distribution of the impurity changes according to the change of the subsequent thermal process, resulting in non-uniform PD formation. In addition, as the impurity implantation and diffusion processes are repeated, the possibility of heavy metals flowing into the PD increases. As a result, a dark current is generated, which weakens the characteristics of the device. In addition to PD, VCCDs produced by the same process are also affected by the same, increasing the dark current, and weakening the ability to control the concentration and profile of impurities. That is, in the solid state imaging device manufactured according to the related art, when the uniformity of the PD or the VCCD decreases and the saturation roughness is exceeded, non-uniformity may occur between the PDs in the device, and the defect may worsen on the screen.

The present invention provides a solid state image pickup device having a structure in which a first P type well is formed deep in an N type substrate to separate the N type substrate into an upper substrate and a lower substrate, and the upper substrate is used as a PD and a VCCD. By preventing VCCD from counter-doping, it minimizes point defects and suppresses dark current and white defects.

According to the present invention, a first P-type well is formed deeply in an N-type substrate to separate the N-type substrate into an upper substrate and a lower substrate, and a second P-type well is formed on the first P-type well in the upper substrate. By controlling the concentration and the spacing of PD and VCCD formed in the portion between the wells and the second P-type wells easily, it is possible to suppress the blooming and to over-flow drain in the vertical direction. To make it easy.

The present invention provides a solid-state imaging device in which a photoelectric conversion unit and a vertical charge transfer region are alternately formed to form a cell array unit, the first conductivity type substrate and the second conductivity type first well formed on the first conductivity type substrate. And a first conductivity type well formed on the second conductivity type well, and a second conductivity type second well formed along the vertical charge transfer region on the second conductivity type first well in the first conductivity type well. And a first conductivity type photoelectric conversion unit formed between the second conductivity type first well in the first conductivity type well, and the first conductivity type upper part of the second conductivity type second well in the first conductivity type well. A first conductivity type vertical charge transfer region formed along a second conductivity type second well, a first insulating film covering an exposed surface of the second well, and an upper portion of the charge transfer region formed on the first insulating film First and second transmission gates, and the first and second transmission gates A second insulating film covering the substrate exposed and trucks, and is on the second insulating film comprises a light shielding layer formed to cover a portion other than the photoelectric conversion portion.

The present invention relates to a method for manufacturing a solid-state imaging device in which a photoelectric conversion unit and a vertical charge transfer region are alternately formed to form a cell array unit. The first conductive substrate, the second conductive first well and the first conductive well are Providing a substrate that is sequentially positioned, forming a second conductive second well formed along a vertical charge transfer region on said second conductive first well in said first conductive well; Forming a first conductivity type photoelectric conversion section between the second conductivity type first wells in the first conductivity type well, and the second conductivity on top of the second conductivity type second wells in the first conductivity type wells Forming a first conductivity type vertical charge transfer region along the type second well, forming a first insulating film covering the exposed surface of the second well, and forming a charge transfer region on the first insulating film. First and second formers located at the top Forming a gate gate, forming a second insulating film covering the first and second transfer gates and the exposed substrate, and forming a light shielding layer on the second insulating film to cover a portion other than the photoelectric conversion portion. Process.

1 is a plan view of a general solid state imaging device

2A through 2E are manufacturing process diagrams of a solid state image pickup device according to the related art.

3A through 3E are manufacturing process diagrams of the solid state image pickup device according to the present invention.

4 is a cross-sectional view of a solid state image pickup device according to the present invention.

FIG. 5 is a potential distribution diagram of the solid state image pickup device shown along AA ′ and BB ′ of FIG. 4.

3A to 3E show a manufacturing process diagram of the solid state image pickup device for explaining the embodiment according to the present invention.

Referring to FIG. 3A, the first P-type well 1PW is formed by deeply injecting and diffusing P-type impurities into the entire region where the CCD operates on the N-type semiconductor substrate. In this case, the first P-type well 1PW may be formed to have a thickness of about 4 to 5 μm. In this case, the implantation energy is increased so that the impurities are deeply implanted into the substrate. The substrate is separated into a lower N-type substrate N2 and an upper N-type substrate N1 to form an NPN junction with the first P-type well 1PW. Subsequently, a P-type impurity is implanted into a portion where the VCCD is to be formed to form a second P-type well 2PW. At this time, the second P-type well 2PW adjusts the implantation energy of the impurity so that it can be located at the upper end of the first P-type well 1PW, and the size thereof is increased. PD is formed between each second P-type well 2PW, and an upper portion of the second P-type well 2PW is a portion where VCCD is to be formed. At this time, the concentration of the initial substrate of the upper N-type substrate N2 is maintained as it is.

The resulting substrate can also be achieved by other processes. That is, a P-type epitaxial layer is grown on the N-type substrate N1 to form a first P-type well 1PW, and an N-type epitaxial layer is grown on the first P-type well 1PW to form PD and VCCD. An N-type well on which the HCCD is to be formed, that is, the upper N-type substrate N2 may be formed.

Referring to FIG. 3B, the PD (PDN) is formed by implanting N-type impurities between a portion where the PD is to be formed, that is, between each second P-type well 2PW of the upper N-type substrate N2. At this time, the concentration of the N-type impurities present in the PD is controlled at the time of impurity implantation so as to have a higher concentration than that of the upper N-type substrate N2. Subsequently, VCCD is formed by implanting high concentration N-type impurities into the upper portion of the second P-type well 2PW of the upper N-type substrate N2 by the same method in which the PD is formed.

Referring to FIG. 3C, a P-type impurity is implanted into a predetermined portion of the substrate to form a channel stop layer CST around the N-type PD (PDN). Then, the first insulating film 32 covering the exposed entire surface of the substrate is formed.

Referring to FIG. 3D, after the first polysilicon layer is deposited and etched on the first insulating layer 32 to form a first transfer gate 33, the first transfer gate 33 is oxidized to form a first transfer gate 33. An oxide insulating film 34 is formed. Subsequently, a second polysilicon layer deposition and etching process is performed to form a second transfer gate 35 positioned on the first transfer gate 33, and then the second transfer gate 35 is oxidized to oxidize the second. The insulating film 36 is formed. Subsequently, a P-type impurity layer (PDP) of the PD is formed by implanting and diffusing the P-type impurity on the surface of the PD,

Referring to FIG. 3E, after forming the second insulating layer 37 covering the exposed entire surface, a metal layer is deposited and etched on the second insulating layer 37 to cover portions except for PD (PDN). 38). Subsequently, an insulating material is deposited on the exposed entire surface of the substrate to form a protective film 39 that protects the substrate.

Referring to Figure 4 showing the cross-sectional structure of the operation of the solid-state imaging device according to the invention produced by the above process as follows.

A first P-type well 1PW having a predetermined thickness is formed at a predetermined position of the N-type substrate, and the substrate is separated into a lower N-type substrate N1 and an upper N-type substrate N2. In the upper N-type substrate N2 above the first P-type well 1PW, a second P-type well 2PW is formed along the N-type VCCD at predetermined intervals. An N-type PD (PDN) is formed between each second P-type well 2PW corresponding to each VCCD. Therefore, PD (PDN) is a region in which N-type impurities are distributed in high concentration, and since PD is formed on the upper N-type substrate in which N-type impurities are distributed in low concentration, in fact, PD is a region in which impurities are distributed in high concentration. (PDN) and the upper N-type substrate N2 which is a low concentration impurity region are combined. As in the conventional structure, the channel stop layer CST is formed around the PD (PDN), and the P-type impurity layer (PDP) of the PD is formed on the surface of the PD (PDN). The first insulating layer 32 covers the substrate having the above-described structure, and the first transfer gate 33 and the second transfer gate 35 are formed on the first insulating layer 32, and the light shielding layer 38 is formed. ) Covers the VCCD portion on the second insulating film 37.

As mentioned, in the above structure, the area of the PD is substantially defined as the interval between the second P-type wells 2PW, so that the area is expanded. That is, the upper N-type substrate N2 doped with low concentration N-type impurities can be used as it is as a PD so that the signal charge can be read. In addition, the contact point with the first P-type well 1PW of the upper N-type substrate N2, which is actually PD, is widened, so that it is easy to OFD vertically through the first P-type well 1PW when excessive electrons are generated. . In addition, smear electrons are less likely to occur due to the expansion of the PD, and even when light enters the side of the second P-type well 2PW, the PD flows into the PD and is treated as signal charge. As described above, since the smear prevention effect is influenced by the extended area of the PD, smear prevention is controlled by appropriate depth and concentration control of the second P-type well 2PW.

The PD is formed at a relatively high surface portion at a higher concentration than the upper N-type substrate N2, whereby the signal charge amount of the PD is increased and it is easy to read the VCCD. Referring to FIG. 5 showing the potential distribution for this portion, in the PD (PD), the potential maximum value is larger than that of the upper N-type substrate N2, and since this value is present in the surface portion, it is difficult to read it by VCCD. It is easy and also easy to increase the signal charge amount of PD.

There is no counter-doped region other than the channel stop layer CST and the P-type impurity layer PDP of the PD. That is, since the PD and the VCCD are not formed by the counter doping, there is no source of the point defect that the conventional technique is good, so that the dark current can be reduced.

The area of the PD in the vertical direction can be adjusted to the depth of the first P-type well 1PW, and the thickness in the vertical direction of the VCCD can be adjusted by the formation of the second P-type well 2PW.

The present invention provides a solid state image pickup device having a structure in which a first P type well is formed deep in an N type substrate to separate the N type substrate into an upper substrate and a lower substrate, and the upper substrate is used as a PD and a VCCD. The VCCD can be prevented from being counter-doped to minimize point defects and to suppress dark currents and white defects. In addition, the present invention can easily control the concentration and spacing of the PD and VCCD formed between the portions of the first P-type well and the second P-type well by the thickness and spacing, thereby suppressing the blooming and in the vertical direction OFD (Over-Flow Drain) is easy. In addition, by the above structure, the effective area of the PD can be increased.

Claims (5)

In the solid-state image pickup device comprising a photoelectric conversion unit and a vertical charge transfer region alternately forming a cell array unit, A first conductivity type substrate, A second conductivity type first well formed on the first conductivity type substrate, A first conductivity type well formed on the second conductivity type well, A second conductivity type second well formed along the vertical charge transfer region on the second conductivity type first well in the first conductivity type well; A first conductivity type photoelectric conversion unit formed between the second conductivity type first well in the first conductivity type well; A first conductivity type vertical charge transfer region formed along the second conductivity type second well in the first conductivity type well on the second conductivity type second well; A first insulating film covering the exposed surface of the second well; First and second transfer gates formed on the charge insulating region on the first insulating layer; A second insulating film covering the first and second transfer gates and the exposed substrate; And a light shielding layer formed on the second insulating layer to cover a portion except the photoelectric conversion unit. The method according to claim 1, And a second conductive channel stop layer formed around the photoelectric conversion portion, and a second conductive impurity layer formed on an upper surface of the photoelectric conversion portion. In the method for manufacturing a solid-state image pickup device comprising a photoelectric conversion unit and a vertical charge transfer region alternately forming a cell array unit, Providing a substrate in which the first conductive substrate, the second conductive first well and the first conductive well are sequentially positioned; Forming a second conductivity type second well formed along the vertical charge transfer region on the second conductivity type first well in the first conductivity type well; Forming a first conductivity type photoelectric conversion section between the second conductivity type first wells in the first conductivity type wells; Forming a first conductivity type vertical charge transfer region along the second conductivity type second well on top of the second conductivity type second well in the first conductivity type well; Forming a first insulating film covering the exposed surface of the second well; Forming first and second transfer gates positioned on the charge insulating region on the first insulating layer; Forming a second insulating film covering the first and second transfer gates and the exposed substrate; And forming a light shielding layer on the second insulating film to cover a portion other than the photoelectric conversion portion. The method according to claim 3, The substrate is formed by injecting a second conductivity type impurity into a first conductive substrate in a predetermined position to form a second conductivity type first well so that the second conductivity type first well is removed from the first conductivity type substrate. 1 Solid state imaging device, characterized in that provided by separating the conductive well. The method according to claim 3, The substrate may be formed by growing a second conductivity type epi layer on a first conductivity type substrate to a predetermined thickness to form the second conductivity type first well, and the first conductivity type epi layer on the second conductivity type first well. And growing the first conductive well to provide a solid state imaging device.

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