KR940003028A - ROM manufacturing method - Google Patents

ROM manufacturing method Download PDF

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Publication number
KR940003028A
KR940003028A KR1019920012598A KR920012598A KR940003028A KR 940003028 A KR940003028 A KR 940003028A KR 1019920012598 A KR1019920012598 A KR 1019920012598A KR 920012598 A KR920012598 A KR 920012598A KR 940003028 A KR940003028 A KR 940003028A
Authority
KR
South Korea
Prior art keywords
protective film
forming
code
gate
ion implantation
Prior art date
Application number
KR1019920012598A
Other languages
Korean (ko)
Inventor
신방주
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920012598A priority Critical patent/KR940003028A/en
Publication of KR940003028A publication Critical patent/KR940003028A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본발명은 마스크롬의 제조방법에 관한 것으로, 게이트와 소오스/드레인을 형성 후 코드 이온 주입하고 보호막을 형성하거나, 보호막가지 형성하고 코드 이온 주입을 함으로써 TAT가 늦고, 높은 에너지의 이온 주입기가 필요하며, 문턱전압 조절이 어려운 종래의 문제점을 개선하기 위한 것이다.The present invention relates to a method for manufacturing a mask rom, and after forming a gate and a source / drain, a code ion implantation and a protective film are formed, or a protective film is formed and a code ion implantation is performed. In order to improve the conventional problem, it is difficult to adjust the threshold voltage.

이와같은 본발명은 보호막 및 패드 공정후 코드 마스크를 이용하여 게이트위의 중간절연막까지 식각하고 코드이온 주입하고 다시 식각된 넉위에 보호막을 SOG률 리프트 오프법을 이용하여 채운것이다.The present invention is to etch the interlayer insulating film on the gate using a code mask after the protective film and pad process, the code ion is implanted, and the protective film is filled on the etched knot by using the SOG rate lift-off method.

따라서, TAT를 향상시키고 공정이 간편해진다.Therefore, TAT is improved and the process is simplified.

Description

롬(ROM)제조방법ROM manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 롬(ROM)공정단면도.2 is a cross-sectional view of a ROM process of the present invention.

Claims (2)

기판에 게이트와 소오스/드레인 영역을 형성하는 공정과, 전면에 중간절연막, 평탄타용 절연막 복수개의 보호막을 차례로 증착하는 공정과. 코드마스크를 이용하여 상기 중간절연막가지 식각하고 코드 이온 주입하는 공정과, 상기 식각된 부위에 보호막을 형성하는 공정으로 이루어짐을 특징으로 하는 롬(ROM)제조방법.Forming a gate and a source / drain region on the substrate; And a process of etching the intermediate insulating layer using a code mask and implanting cord ions, and forming a protective layer on the etched portion. 제1항에 있어서, 상기 식각된 부위의 보호막 형성방법은 SOG를 리프트 오프 방법으로 헝성함을 특징으로 하는 롬(ROM) 제조방법.The method of claim 1, wherein the forming of the protective layer on the etched portion comprises forming SOG by a lift-off method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012598A 1992-07-15 1992-07-15 ROM manufacturing method KR940003028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012598A KR940003028A (en) 1992-07-15 1992-07-15 ROM manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012598A KR940003028A (en) 1992-07-15 1992-07-15 ROM manufacturing method

Publications (1)

Publication Number Publication Date
KR940003028A true KR940003028A (en) 1994-02-19

Family

ID=67147035

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920012598A KR940003028A (en) 1992-07-15 1992-07-15 ROM manufacturing method

Country Status (1)

Country Link
KR (1) KR940003028A (en)

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