KR940002834Y1 - Automatic frequency control circuit - Google Patents

Automatic frequency control circuit Download PDF

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KR940002834Y1
KR940002834Y1 KR2019890015414U KR890015414U KR940002834Y1 KR 940002834 Y1 KR940002834 Y1 KR 940002834Y1 KR 2019890015414 U KR2019890015414 U KR 2019890015414U KR 890015414 U KR890015414 U KR 890015414U KR 940002834 Y1 KR940002834 Y1 KR 940002834Y1
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South Korea
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signal
oscillator
gate
frequency control
automatic frequency
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KR2019890015414U
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Korean (ko)
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KR910007892U (en
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이주석
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

내용 없음.No content.

Description

자동 주파수 제어회로Automatic frequency control circuit

제 1 도는 종래의 자동 주파수 제어회로도.1 is a conventional automatic frequency control circuit diagram.

제 2 도는 종래 자동 주파수 제어회로의 타이밍 챠트도.2 is a timing chart of a conventional automatic frequency control circuit.

제 3 도는 본 고안에 따른 자동 주파수 제어회로도.3 is an automatic frequency control circuit diagram according to the present invention.

제 4 도는 본 고안에 따른 자동 주파수 제어회로의 타이밍 챠트도.4 is a timing chart of an automatic frequency control circuit according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 160fH발진기 2 : 1/160분주기1: 160fH oscillator 2: 1/160 min cycle

3 : 자동주파수 에러필터 4 : 후수평 동기신호 발생회로3: automatic frequency error filter 4: rear horizontal synchronization signal generating circuit

5 : 전수평 동기신호 발생회 SW1:에러전류스위치5: Full horizontal synchronization signal generation time SW 1 : Error current switch

SW2:에러 전류 스위치 G1, G2: 앤드게이트SW 2 : Error current switch G 1 , G 2 : end gate

G3: 인버터 G4: 오아게이트G 3 : Inverter G 4 : Oagate

본 고안은 VCR에 관한 것으로 특히 칼라신호 처리에 적당하도록 한 자동 주파수 제어회로에 관한 것이다.The present invention relates to a VCR, and more particularly to an automatic frequency control circuit suitable for color signal processing.

제 1 도에 도시된 종래의 자동 주파수 제어(AFC) 회로의 구성 및 동작상태는 다음과 같다.The configuration and operating state of the conventional automatic frequency control (AFC) circuit shown in FIG. 1 are as follows.

160fH발진기(1)의 출력은 카운트로 구성된 1/160분주기(2)에 입력되고 1/160분주기(2)의 출력은 앤드게이트(G1)의 한측입력이 되는 동시에 인버터(G3)를 거쳐 앤드게이트(G2)의 한측 입력이 되며, 수평동기신호(H)는 앤드게이트(G1, G2)의 나머지 한측 입력이 되고 앤드게이트(G1)의 출력은에러전류 스위치(SW1)를 동작시키고 앤드게이트(G2)의 출력은에러전류 스위치(SW2)를 동작시키며, 또 앤드게이트(G1, G2)의 출력은 오아게이트(G4)를 통해 스위치(SW3)를 제어하여 자동 주파수 제어 에러필터(3)에 바이어스를 제공하고 자동 주파수 제어 에러필터(3)의 출력은 160fH발진기(1)로 피이드백 하도록 구성된다.The output of the 160fH oscillator 1 is input to a 1/160 frequency divider 2 composed of counts, and the output of the 1/160 frequency divider 2 becomes one input of the end gate G 1 and at the same time the inverter G 3 . One side input of the AND gate (G 2 ) through, and the horizontal synchronization signal (H) is the other side input of the AND gate (G 1 , G 2 ) and the output of the AND gate (G 1 ) The error current switch (SW 1 ) is operated and the output of the AND gate (G 2 ) The error current switch SW 2 is operated, and the outputs of the AND gates G 1 and G 2 control the switch SW 3 through the oragate G 4 to bias the automatic frequency control error filter 3. And the output of the automatic frequency control error filter (3) is configured to feed back to the 160fH oscillator (1).

상기 구성 회로의 동작상태를 설명하면, 발진기(1)의 160fH(160수평동기 신호 주파수)발진 신호를 1/160분주기(2)에서 카운트 다운하면 'fH'(수평동기신호 주파수)신호가 (제 2 도의 (a)파형)된다.Referring to the operation state of the configuration circuit, when the 160fH (160 horizontal synchronizing signal frequency) oscillation signal of the oscillator 1 counts down in the 1/160 frequency divider 2, the 'fH' (horizontal synchronizing signal frequency) signal is ( (A) waveform of FIG. 2).

이 신호와 입력신호에서 동기신호를 분리한 신호 수평 동기신호(제 2 도의 (b)파형)(H)와 앤드게이트(G1)에서 앤드시켜에러전류 스위치(SW1)를 '온'시키고 1/160분주기(2)에서의 'fH'신호를 인버터(G3)에 의해 반전한 신호와 수평동기신호(H)를 앤드시켜에러전류 스위치(SW2)를 '온'시키면, 제 2b 도의 신호가 160fH발진신호보다 위상이 빠르거나 늦거나 일치할 때 (록킹시) 생성된 에러 전류의 출력이 제 2 도의 (C)파형과 같이방향방향으로 나타난다.The signal is synchronized with the signal horizontal synchronizing signal (waveform in FIG. 2 (b)) H and the AND gate G 1 which separate the synchronizing signal from the input signal. The error current switch SW 1 is turned on and the signal 'fH' of the 1/160 divider 2 is inverted by the inverter G 3 and the horizontal synchronous signal H When the error current switch SW 2 is turned on, the output of the error current generated when the signal of FIG. 2b is out of phase, later or coincides with the 160fH oscillation signal (at the time of locking) is compared with the waveform of FIG. together direction Appears in the direction.

이것이 자동 주파수 제어(AFC) 에러필터(3)에 의해 평활된 전압(제 2 도의 (d)파형)에 따라 160fH발진기(1)에 피이드백 되어 발진 주파수를 조정함으로서 160fH발진기(1)의 주파수가 입력 수평동기신호(H)와 일치한다.This is fed back to the 160fH oscillator 1 according to the voltage smoothed by the automatic frequency control (AFC) error filter 3 (d waveform in FIG. 2) to adjust the oscillation frequency so that the frequency of the 160fH oscillator 1 is adjusted. Coincides with the input horizontal synchronization signal (H).

그런데 상기와 같은 종래 회로에서는 160fH발진기의 출력와 입력신호에 의해 수평동기 신호(H)의 주파수가 일치하는 록킹 시에도방향과방향의 에러전류가 흐르므로 에러전압이 발생하게 되고 이 에러전압에 의해 160fH발진기의 주파수가 흔들리므로 메인 콘버터(Main Converter)가 가해지는 4.21MHZ의 서브-캐리어가 흔들려 화면의 칼라신호가 떨리게 되는 단점이 있었다.However, in the conventional circuit as described above, even when the frequency of the horizontal synchronization signal (H) coincides by the output and input signal of the 160fH oscillator Direction and An error voltage is generated because an error current flows in the direction, and the frequency of the 160fH oscillator is shaken by this error voltage, causing the sub-carrier of 4.21MHZ to which the main converter is applied to shake the color signal on the screen. There was this.

본 고안은 이러한 단점을 해결하기 위해 안출된 것으로 첨부 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention has been devised to solve these disadvantages and will be described in detail with reference to the accompanying drawings.

먼저, 제 3 도에서 그 구성을 상세히 설명하면, 160fH발진기(1)의 160fH발진 신호는 카운터로 구성되는 1/160분주기(2)로 인가되고 1/160분주기(2)의 출력은 앤드게이트(G1)의 한측 입력으로 인가되는 동시에 인버터(G3)를 통해 앤드게이트(G2)의 한측입력으로 인가되며 영상입력신호에서 분리된 수평동기신호(H)는 전, 후 수평동기신호발생회로(5, 4)로 동시 인가되며 후(後)수평동기신호발생회로(4)에서 발생된 후 수평동기신호는 앤드게이트(G1)의 나머지 한측입력이되고 전(前)수평동기신호(5)에서 발생된 전수평동기신호는 앤드게이트(G2)의 나머지 한측 입력에 연결되며, 앤드게이트(G1)의 출력은에러전류 스위치(SW1)를 동작시키고 앤드게이트(G2)의 출력은에러전류 스위치(SW2)를 동작시키고 또 앤드게이트(G1, G2)의 각 출력은 오아게이트(G4)의 입력이 되고 오아게이트(G4)의 출력은 스위치(SW3)를 동작시켜 자동주파수 제어 에러필터(3)에 바이어스를 제공하고 자동주파수 제어에러 필터(3)의 출력은 160fH발진기(1)로 피이드백하도록 구성된다.First, the configuration of FIG. 3 is described in detail. The 160fH oscillation signal of the 160fH oscillator 1 is applied to a 1/160 frequency divider 2 composed of a counter and the output of the 1/160 frequency divider 2 is The horizontal synchronous signal H, which is applied to one side input of the gate G 1 and is simultaneously applied to one side input of the AND gate G 2 through the inverter G 3 , is separated from the image input signal. The horizontal synchronous signal is applied to the generating circuits 5 and 4 simultaneously and generated from the later horizontal synchronous signal generating circuit 4, and the horizontal synchronous signal becomes the other side input of the AND gate G 1 and the previous horizontal synchronous signal. The full horizontal synchronizing signal generated at (5) is connected to the other input of the AND gate G 2 , and the output of the AND gate G 1 is The error current switch (SW 1 ) is operated and the output of the AND gate (G 2 ) Error operating the current switch (SW 2) and also the AND gate (G 1, G 2) of the respective output Iowa gate (G 4) and the input of the Iowa gate (G 4) output operates a switch (SW 3) of To provide a bias to the automatic frequency control error filter 3 and the output of the automatic frequency control error filter 3 feeds back to the 160fH oscillator 1.

상기 구성회로의 동작상태를 설명하면, 160fH발진기(1)에서 출력된 160fH발진기(1)는 1/160분주기(2)에서 카운터에의해 160분주되어 제 4 도의 (a)파형과 같은 분주신호로 발생된다.Referring to the operation state of the configuration circuit, the 160fH oscillator 1 outputted from the 160fH oscillator 1 is divided by the counter in the 1/160 frequency divider 2 by 160 and divided into a signal such as the waveform (a) of FIG. Is caused by.

들어오는 입력신호에서 수평동기신호(H)를 분리하여 (b파형) 입력 수평동기신호에 의해 생성된 수평동기신호(H)를 만들고 이것을 전 수평동기신호 발생회로(5)와 후수평동기 신호 발생회로(4)로 인가하여 수평동기신호의 폭을 반으로 나누어 전 수평동기신호와 후 수평동기신호를 제 4 도의 (C)파형과 (d)파형과 같이 만든다.Separating the horizontal synchronizing signal (H) from the incoming input signal (b waveform) to create a horizontal synchronizing signal (H) generated by the input horizontal synchronizing signal (H), and the horizontal synchronizing signal generating circuit (5) and the rear horizontal synchronizing signal generating circuit. In (4), the width of the horizontal synchronous signal is divided in half so that the front horizontal synchronous signal and the rear horizontal synchronous signal are made like the waveforms (C) and (d) in FIG.

후 수평동기 신호(제 3 도의 (d)파형)와 1/160분주기(2)에서 1/160분주된 신호(제 4 도의 (a)파형)를 앤드게이트(G1)에서 앤드하여에러전류 스위치(SW1)를 '온'시켜에러전류가 자동주파수 제어필터(3)에 흐르게하고 전수평동기신호(제 3 도의 (c)파형)와 1/160분주된 신호가 인버터(G3)를 통해 반전된 신호를 앤드게이트(G2)에서 앤드하여에러전류 스위치(SW2)를 '온'시켜에러전류를 흐르게 하면 제 4e 도와 같이 된다.The horizontal synchronous signal (waveform in FIG. 3d) and the signal 1/160 divided in the 1/160 frequency divider 2 (waveform (a) in FIG. 4) are ANDed at the AND gate G 1 . Turn on the error current switch (SW 1 ) The error current flows to the automatic frequency control filter 3, and the AND gate (G 2 ) converts a signal in which the total horizontal synchronization signal (waveform in FIG. 3 (c)) and the 1/160 divided signal are inverted through the inverter G 3 . From) Turn on the error current switch (SW 2 ) When the error current flows, it becomes like the 4e diagram.

즉 수평동기신호의 위상이 160fH발진 위상보다 빠른 경우는에러전류를 자동주파수 제어에러필터(3)에 흐르게 하고 수평동기신호의 위상이 160fH발진 위상보다 느린 경우는 반대로 자동주파수 제어에러 필터(3)에에러전류 흐르게 하여 자동주파수제어 에러필터(3)에서 생성된 에러전압이 160fH발진기(1)로 피이드백되어 160fH발진기(1)의 발진주파수를 제어하게 된다.In other words, if the phase of the horizontal synchronization signal is faster than the 160 fH oscillation phase, If an error current flows to the automatic frequency control error filter 3 and the phase of the horizontal synchronous signal is slower than the 160 fH oscillation phase, the automatic frequency control error filter 3 is reversed. The error current flows and the error voltage generated by the automatic frequency control error filter 3 is fed back to the 160fH oscillator 1 to control the oscillation frequency of the 160fH oscillator 1.

주파수가 같은 경우에는 제 4 도의 III과 같이 에러전류가 발생하지 않는다.If the frequencies are the same, an error current does not occur as shown in FIG.

따라서 본 고안은 160fH발진기의 주파수와 수평동기신호(H)의 주파수가 일치했을 경우(록킹시) 에러전압이 발생하지 않아 160fH발진기의 주파수가 흔들리는 현상이 제거되므로 보다 안정된 화면을 얻을 수 있는 효과가 있다.Therefore, when the frequency of 160fH oscillator and the frequency of horizontal synchronizing signal (H) coincide (locking), the error voltage does not occur and the frequency of 160fH oscillator is eliminated, which makes it possible to obtain a more stable screen. have.

Claims (1)

160fH발진 신호를 얻어내는 160fH발진기(1)와, 상기 160fH발진기(1)의 160fH발진기(1)를 1/160 분주하는 1/160분주기(2)와, 입력신호에서 분리된 수평동기신호(H)의 펄스폭을 반으로 나누어 전수평동기신호와 후수평동기신호를 발생하는 전, 후 수평동기신호 발생회로(5, 4)와, 상기 후수평동기신호발생회로(4)에서 발생된 후수평동기신호와 1/160분주기(2)의 출력신호를 앤드하여에러전류 스위치(SW)를 동작시키는 앤드게이트(G1)와, 전수평동기신호발생회로(5)의 전수평동기신호와 인버터(G3)에 의해 반전된 1/160분주기(2)의 출력신호를 앤드하여에러전류 스위치(SW2)를 동작시키는 앤드게이트(G2)와, 상기 앤드게이트(G1, G2)의 출력을 오아하여 자동주파수 제어에러필터(3)에 바이어스를 제공하는 오아게이트(G4)와,에러전류와에러전류를 평활하고 그 출력을 상기 160fH발진기(1)로 피이드백하여 160fH발진기(1) 주파수를 제어하는 자동주파수 제어에러필터(3)를 포함하여 구성된 것을 특징으로 하는 자동 주파수 제어회로.A 160 fH oscillator 1 for obtaining a 160 fH oscillation signal, a 1/160 divider 2 for dividing a 160 fH oscillator 1 of the 160 fH oscillator 1 1/160, and a horizontal synchronous signal separated from an input signal ( Generated by the horizontal and horizontal synchronization signal generating circuits 5 and 4 and the rear horizontal and synchronous signal generating circuit 4 generating the full horizontal synchronization signal and the rear horizontal synchronization signal by dividing the pulse width of H) by half. The horizontal synchronization signal and the output signal of the 1/160 divider (2) The AND gate G 1 for operating the error current switch SW, and the 1/160 divider 2 inverted by the full horizontal synchronization signal generation circuit 5 and the inverter G 3 . And output signal An AND gate G 2 for operating the error current switch SW 2 and an OR gate G for biasing the output of the AND gates G 1 and G 2 to provide a bias to the automatic frequency control error filter 3. 4 ) and, Error current and And an automatic frequency control error filter (3) for smoothing the error current and feeding the output back to the 160fH oscillator (1) to control the frequency of the 160fH oscillator (1).
KR2019890015414U 1989-10-23 1989-10-23 Automatic frequency control circuit KR940002834Y1 (en)

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KR910007892U KR910007892U (en) 1991-05-31
KR940002834Y1 true KR940002834Y1 (en) 1994-04-23

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KR100481977B1 (en) * 2001-11-21 2005-04-20 대흥아이엔디 주식회사 Cutting Machine

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KR100230768B1 (en) * 1991-11-11 1999-11-15 구자홍 Digitron driving method for vcr

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100481977B1 (en) * 2001-11-21 2005-04-20 대흥아이엔디 주식회사 Cutting Machine

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