KR940001428B1 - Method for fabricating a ldd type eprom - Google Patents

Method for fabricating a ldd type eprom

Info

Publication number
KR940001428B1
KR940001428B1 KR9106483A KR910006483A KR940001428B1 KR 940001428 B1 KR940001428 B1 KR 940001428B1 KR 9106483 A KR9106483 A KR 9106483A KR 910006483 A KR910006483 A KR 910006483A KR 940001428 B1 KR940001428 B1 KR 940001428B1
Authority
KR
South Korea
Prior art keywords
gate
fabricating
floating gate
layer
injecting
Prior art date
Application number
KR9106483A
Other languages
Korean (ko)
Other versions
KR920020730A (en
Inventor
Byong-Jin An
Yun-Han Kim
Jong-U Kim
Original Assignee
Hyundai Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Co Ltd filed Critical Hyundai Electronics Co Ltd
Priority to KR9106483A priority Critical patent/KR940001428B1/en
Publication of KR920020730A publication Critical patent/KR920020730A/en
Application granted granted Critical
Publication of KR940001428B1 publication Critical patent/KR940001428B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A gate oxide layer (2) and a floating gate poly silicon layer (3a) are formed on a silicon substrate (1) to make a floating gate (3) with a mask pattern process. An inner isolating layer (4) is formed on the floating gate (3) to make a gate poly silicon layer (5a); the gate (5) is fabricated by using the etching process. A source (7) and a drain (7') are constructed by injecting a high density impurity material on the silicon substrate (1). The LDD region (8) is built by injecting a low density impurity material on the substrate (1).
KR9106483A 1991-04-23 1991-04-23 Method for fabricating a ldd type eprom KR940001428B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR9106483A KR940001428B1 (en) 1991-04-23 1991-04-23 Method for fabricating a ldd type eprom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR9106483A KR940001428B1 (en) 1991-04-23 1991-04-23 Method for fabricating a ldd type eprom

Publications (2)

Publication Number Publication Date
KR920020730A KR920020730A (en) 1992-11-21
KR940001428B1 true KR940001428B1 (en) 1994-02-23

Family

ID=19313573

Family Applications (1)

Application Number Title Priority Date Filing Date
KR9106483A KR940001428B1 (en) 1991-04-23 1991-04-23 Method for fabricating a ldd type eprom

Country Status (1)

Country Link
KR (1) KR940001428B1 (en)

Also Published As

Publication number Publication date
KR920020730A (en) 1992-11-21

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