KR940000746B1 - Chip bonding method of semiconductor - Google Patents

Chip bonding method of semiconductor Download PDF

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Publication number
KR940000746B1
KR940000746B1 KR1019900020450A KR900020450A KR940000746B1 KR 940000746 B1 KR940000746 B1 KR 940000746B1 KR 1019900020450 A KR1019900020450 A KR 1019900020450A KR 900020450 A KR900020450 A KR 900020450A KR 940000746 B1 KR940000746 B1 KR 940000746B1
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South Korea
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chip
die pad
bonding method
semiconductor device
package
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KR1019900020450A
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Korean (ko)
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KR920013648A (en
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김진호
안재문
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삼성전자 주식회사
김광호
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Publication of KR920013648A publication Critical patent/KR920013648A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

Abstract

The method is for bonding chips on die pads of the IC manufacturing apparatus. The chip bonding method distributes the pressure generated on the lower face of the die pad so that it can prevents gaps or cracks from generating between the die pad and a package. The chip bonding method comprises forming adhesive agent (13) in a dot type and adhering the chip (12) to the die pad (11); pressing the chip (12) toward the die pad (11) and making a buffer space (18) between the adhesive agent (13); and bonding the chip (12) and a lead (14) with golden wire (15) and cutting/bending the lead (14).

Description

반도체장치의 칩 본딩방법Chip bonding method of semiconductor device

제1도는 일반적인 반도체장치의 단면구조도.1 is a cross-sectional structure diagram of a general semiconductor device.

제2도(a)는 종래의 칩 본딩 방법을 나타낸 분리사시도, (b)는 이 발명에 따라 칩 본딩된 상태의 단면도.Figure 2 (a) is an exploded perspective view showing a conventional chip bonding method, (b) is a cross-sectional view of the chip bonded state according to the present invention.

제3도 이 발명에 따른 반도체장치의 단면구조도.3 is a cross-sectional structure diagram of a semiconductor device according to the present invention.

제4도(a)는 이 발명에 따른 칩 본딩 방법을 나타낸 분리사시도, (b)는 이 발명에 따라 칩 본딩된 상태의 단면도.Figure 4 (a) is an exploded perspective view showing a chip bonding method according to the present invention, (b) is a cross-sectional view of the chip bonded state according to the present invention.

제5도(a)는 이 발명의 다른 실시예에 따른 칩 본딩 방법을 나타낸 분리사시도, (b) 이 발명의 다른 실시예에 따라 칩 본딩된 상태의 단면도.Figure 5 (a) is an exploded perspective view showing a chip bonding method according to another embodiment of the present invention, (b) a cross-sectional view of the chip bonded state according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,11,21 : 다이패드 2,12,22 : 칩1,11,21: die pad 2,12,22: chip

3,13,23 : 접착제 4,14 : 리이드3,13,23: adhesive 4,14: lead

5,15 : 금와이어 6,16 : 패키지5,15: gold wire 6,16: package

7,17 : 반도체장치 18,18a,18b : 완충공간부7,17: semiconductor device 18,18a, 18b: buffer space portion

21a : 장공21a: longevity

이 발명은 반도체장치에 관한 것으로서, 더욱 상세하게는 반도체장치의 다이패드에 칩을 부착시키기 위한 칩 본딩 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a chip bonding method for attaching a chip to a die pad of a semiconductor device.

일반적으로 반도체장치는 제1도에서와 같이, 다이패드(1) 상면에 칩(2)을 접착제(3)로 부착하고, 상기 칩(2)과 양측의 리이드(4)를 금와이어(5)로 본딩한 다음 콤파운드로 패키지(6)를 성형하여 반도체장치(7)를 만들게 된다. 이대 종래의 칩 본딩 방법은 제2도의 (a),(b)에서와 같이, 다이패드(1)에 칩(2)을 부착함에 있어 접착제(3)는 주로 은(Ag)을 함유하는 에폭시(Epoxy)를 사용하여, 접착제(3)를 다이패드(1)의 상면에 방사형태의 도트(Dot)로 조밀하게 형성한 다음 칩(2)을 다이패드(1) 상면에 부착시키게 되면, 도트형태의 접착제(3)가 눌리어 칩(2)의 전면에 걸쳐 퍼지면서 다이패드(1)와 부착되는 본딩방법이었다. 그러나 상기와 같은 칩 본딩 방법에 의해 제작된 반도체장치는 패키지(6) 성형시 콤파운드와 다이패드(1)와의 재질차로 열팽창이 다르게 됨에 따라 습기가 패키지(6)내에 존재하게 되고, 이로인해 반도체장치(7)의 실장시에 발생하는 고온으로써 패키지(6)내의 다이패드(1) 저면에 존재하고 있던 습기가 수증기압으로 변하게 된다. 따라서 다이패드(1)의 저면에서 압력이 발생하게 되고, 제2도의 (b)에서와 같이 칩(2)과 다이패드(1) 사이에는 접착제(3)로 막혀 있기 때문에 압력이 하방으로 작용하여 다이패드(1)와 패키지(6) 사이에 틈이 발생하거나 다이패드(1)의 패키지(6)와의 접촉부위에 크랙이 발생하게 되어 불량품 발생시의 주요원인으로 되는 문제점이 있었다.In general, as shown in FIG. 1, the semiconductor device attaches the chip 2 to the upper surface of the die pad 1 with an adhesive 3, and attaches the chip 2 and the leads 4 on both sides to the gold wire 5, respectively. The semiconductor device 7 is formed by bonding the wafer and then molding the package 6 into a compound. In the conventional conventional chip bonding method, as shown in (a) and (b) of FIG. 2, in attaching the chip 2 to the die pad 1, the adhesive 3 mainly contains epoxy (Ag) containing epoxy ( Using epoxy, the adhesive 3 is densely formed on the upper surface of the die pad 1 with a radial dot, and then the chip 2 is attached to the upper surface of the die pad 1, and then the dot shape is formed. It was a bonding method in which the adhesive 3 was attached to the die pad 1 while spreading over the entire surface of the pressed chip 2. However, in the semiconductor device manufactured by the chip bonding method as described above, moisture is present in the package 6 as the thermal expansion is different due to the material difference between the compound and the die pad 1 when the package 6 is formed. Due to the high temperature generated at the time of mounting (7), the moisture existing on the bottom surface of the die pad 1 in the package 6 is changed to the water vapor pressure. Therefore, pressure is generated at the bottom of the die pad 1, and as shown in (b) of FIG. 2, the pressure is acted downward because the adhesive 3 is blocked between the chip 2 and the die pad 1. There is a problem that a gap occurs between the die pad 1 and the package 6 or a crack occurs at the contact portion of the die pad 1 with the package 6, which is a major cause of defective products.

이 발명은 상기의 문제점을 감안하여 이루어진 것으로서, 이 발명의 목적은 반도체장치의 실장시 고온으로 발생하는 패키지내의 수증기압에 의해 다이패드 저면에서 발생하는 압력을 분산시킬 수 있도록 다이패드에 칩을 본딩하는 방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to bond a chip to a die pad so as to disperse the pressure generated at the bottom of the die pad by the water vapor pressure in the package generated at a high temperature when the semiconductor device is mounted. To provide a method.

상기의 목적을 달성하기 위한 이 발명의 특징은, 다이패드상에 접착제를 도트형태로 부착하여 칩을 본딩시키는 반도체장치의 칩 본딩 방법에 있어서, 상기 반도체장치의 실장시 패키지내의 다이패드 저면에서 발생하는 압력을 분산시킬 수 있는 완충공간부가 칩과 다이패드 사이에 형성되도록 도트형태의 접착제를 다이패드의 테두리와 수직, 수평방향으로만 형성하여 칩을 부착하는 반도체장치의 칩 본딩 방법을 제공하는데 있다.A feature of this invention for achieving the above object is a chip bonding method of a semiconductor device in which a chip is bonded by attaching an adhesive on a die pad in the form of dots, which occurs on the bottom surface of a die pad in a package when the semiconductor device is mounted. The present invention provides a chip bonding method of a semiconductor device in which a dot-shaped adhesive is formed only vertically and horizontally with the edge of a die pad so that a buffer space portion capable of distributing pressure can be formed between the chip and the die pad. .

이하, 이 발명의 실시예를 첨부도면에 의하여 상세하게 설명한다. 제3도 및 제4도의 (a),(b)는 이 발명에 따른 반도체장치를 나타낸 것으로서, 다이패드(11)상의 테두리에 반도체 CMIP을 접착가능한 모든 접착제(13)를 도트(Dot)형태로 형성하고, 칩(12)을 다이패드(11)상에 부착한다. 따라서 제4도의 (b)와 같이 다이패드(11)상의 접착제(13)가 눌리면서 칩(12)은 다이패드(11)에 부착됨과 동시에 접착제(130 사이에 완충공간부(18)가 형성된다. 그리고 제3도와 같이 칩(12)과 리이드(14)와를 금와이어(15)로 본딩하고 콤파운드로 패키지(16)를 성형한 다음 리이드(14)의 절단 및 절곡과정을 거침으로써 반도체장치(17)가 제조된다. 또한, 제5도의 (a),(b)는 이 발명의 다른 실시예를 나타낸 것으로서, 칩(22)의 본딩방법에 있어서, 다이패드(21)의 중앙부에 장공(21a)이 형성된 경우에는 제5도의 (a)에서와 같이 장공(21a)을 기준으로 2개의 사각형상으로 테두리부위만 접착제(23)를 형성하여 칩(22)을 다이패드(21)에 부착시킴으로써 접착제(23)사이에 완충공간부(28a)(28b)가 형성되도록 한다.DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of this invention will be described in detail with the accompanying drawings. (A) and (b) of FIG. 3 and FIG. 4 show the semiconductor device according to the present invention, in which all adhesives 13 capable of adhering the semiconductor CMIP to the edges on the die pad 11 are formed in dots. The chip 12 is formed on the die pad 11. Therefore, as shown in FIG. 4B, the adhesive 12 on the die pad 11 is pressed and the chip 12 is attached to the die pad 11, and the buffer space 18 is formed between the adhesive 130. As shown in FIG. 3, the chip 12 and the lead 14 are bonded to the gold wire 15, the package 16 is formed into a compound, and then the cutting and bending of the lead 14 are performed. In addition, (a) and (b) of FIG. 5 show another embodiment of the present invention, in the bonding method of the chip 22, the long hole 21a is formed at the center of the die pad 21. When formed, the adhesive 23 is formed by attaching the chip 22 to the die pad 21 by forming the adhesive 23 only at two rims based on the long hole 21a, as shown in FIG. The buffer spaces 28a and 28b are formed therebetween.

이와같은 이 발명은 다이패드(11)(21)에 칩(12)(22)을 본딩하는 공정에서, 제4도의 (b) 및 제5도의 (b)에서와 같이 다이패드(11)(21)와 칩(12)(22) 사이에 완충공간부 (18)(18a)(18b)가 형성되도록 접착제(13)(23)를 부착함으로써, 패키지(16)의 성형시 다이패드(11)(21)와 패키지(16)와의 재질차이로 인해 패키지(16)내에 존재하게 된 습기가 반도체장치(17)의 실장시 고온에 의해 습기가 증기압으로 변하여 다이패드(11)(21)의 저면에서 압력을 발생시켜도 완충공간부(18)(18a)(18b)에 의해 역방향으로 작용하는 압력이 발생됨으로써 상기의 압력들이 서로 상쇄되어 증기압에 의한 압력이 미약해지게 되는 것이다. 따라서 다이패드(11)(21)와 결합되는 부위 패키지(16)에 크랙이 생기게 되는 것을 방지할 수 있게 되는 것이다.In the present invention as described above, in the process of bonding the chips 12 and 22 to the die pads 11 and 21, the die pads 11 and 21 are as shown in FIGS. 4B and 5B. ), The adhesive pads 13 and 23 are attached so that the buffer space portions 18, 18a and 18b are formed between the chip 12 and the chip 22, and the die pad 11 (in forming the package 16). Due to the difference in material between the package 16 and the package 16, the moisture present in the package 16 changes to vapor pressure due to the high temperature when the semiconductor device 17 is mounted, and the pressure at the bottom of the die pads 11 and 21 is reduced. Even if the pressure is generated, the pressure acting in the reverse direction by the buffer spaces 18, 18a and 18b is generated, so that the above pressures cancel each other and the pressure due to the vapor pressure is weakened. Therefore, cracks may be prevented from occurring in the site package 16 coupled to the die pads 11 and 21.

이상에서와 같이 이 발명에 의하면, 반도체장치의 칩 본딩 방법에 있어서, 다이패드와 칩 사이에 완충공간부가 형성되도록 다이패드에 칩이 본딩됨으로써 반도체장치의 실장시 패키지내의 다이패드 저면에서 발생하는 증기압을 상기 완충공간부로서 증기압이 미약해지게 되어 크랙으로 인한 불량을 줄일 수 있는 효과가 있다.As described above, according to the present invention, in the chip bonding method of a semiconductor device, the chip is bonded to the die pad so that a buffer space is formed between the die pad and the chip, and thus the vapor pressure generated at the bottom of the die pad in the package when the semiconductor device is mounted. As the buffer space portion has a weak vapor pressure has an effect that can reduce the defects due to cracks.

Claims (1)

다이패드(11)상에 접착제(13)를 도트형태로 부착하여 칩(12)을 본딩시키는 반도체장치의 칩 본딩 방법에 있어서, 상기 반도체장치(17)의 실장시 패키지(16)내의 다이패드(11) 저면에서 발생하는 압력을 분산시킬 수 있는 완충공간부(18)가 칩(12)과 다이패드(11) 사이에 형성되도록 도트형태의 접착제(13)를 다이패드(11) 테두리와 수직, 수평방향으로만 형성하여 칩(12)을 부착하는 반도체장치의 칩 본딩 방법.In the chip bonding method of the semiconductor device which bonds the chip | tip 12 by attaching the adhesive agent 13 in the shape of a dot on the die pad 11, The die pad in the package 16 when the said semiconductor device 17 is mounted ( 11) the dot-shaped adhesive 13 is perpendicular to the edge of the die pad 11 so that a buffer space 18 is formed between the chip 12 and the die pad 11 to disperse the pressure generated at the bottom. A chip bonding method of a semiconductor device which is formed only in a horizontal direction to attach a chip (12).
KR1019900020450A 1990-12-13 1990-12-13 Chip bonding method of semiconductor KR940000746B1 (en)

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