KR930024183A - Patterning method of thin film transistor - Google Patents
Patterning method of thin film transistor Download PDFInfo
- Publication number
- KR930024183A KR930024183A KR1019920007707A KR920007707A KR930024183A KR 930024183 A KR930024183 A KR 930024183A KR 1019920007707 A KR1019920007707 A KR 1019920007707A KR 920007707 A KR920007707 A KR 920007707A KR 930024183 A KR930024183 A KR 930024183A
- Authority
- KR
- South Korea
- Prior art keywords
- nitride film
- thin film
- film transistor
- poly
- depositing
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 5
- 238000000034 method Methods 0.000 title claims abstract description 4
- 238000000059 patterning Methods 0.000 title claims description 3
- 239000010408 film Substances 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
박막 트랜지스터(Thin Film Transistor)의 폴리 채널 패턴 형성시 벌크 트랜지스터의 절연 공법을 이용하여, 폴리 채널 상부에 질화막을 디포지션시키며, 마스크 패턴을 이용하여 상기 질화막을 식각한 후 열산화공정을 거침으로써, 폴리층하부의 에지 단면이 유연하게 되어, 누설 전류원을 줄이며, 온전류를 증가시켜 박막 트랜지스터의 특성을 향상시킬 수 있다.When forming a poly channel pattern of a thin film transistor, a nitride film is deposited on the poly channel using an insulating method of a bulk transistor, and the nitride film is etched using a mask pattern and then thermally oxidized. The edge cross section of the lower poly layer can be made flexible, thereby reducing the leakage current source and increasing the on-current, thereby improving the characteristics of the thin film transistor.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2a도는 본 발명의 박막 트랜지스터의 패터닝 방법에 의해 실리콘기판 상부에 폴리케이트 및 게이트 산화막 및 폴리 채널을 순차적으로 디포지션시키는 단계를 나타내는 반도체 소자의 단면도, 제2b도는 제2a도에서 도시된 폴리 채널 상부에 얇은 산화막 및 질화막을 디포지션시키는 단계를 나타내는 반도체 소자의 단면도, 제2c도는 제2b도의 질화막 상부에 포토레지스트 층을 증착시킨 후, 마스크패턴을 형성하여, 그 하부의 질화막 및 산화막을 식각하는 단계를 나타내는 반도체 소자의 단면도, 제2d도는 제2c도에 도시된 잔존 포토레지스트 층을 제거하는 단계를 나타내는 반도체 소자의 단면도, 제2e도는 제2d도에 도시된 잔존 질화막을 제거하는 단계를 나타내는 반도체 소자의 단면도.FIG. 2A is a cross-sectional view of a semiconductor device illustrating a step of sequentially depositing a polyate and gate oxide film and a poly channel on a silicon substrate by a method of patterning a thin film transistor of the present invention, FIG. 2B is a poly channel shown in FIG. 2A A cross-sectional view of a semiconductor device showing a step of depositing a thin oxide film and a nitride film on the upper part, FIG. 2C is a photoresist layer deposited on the nitride film of FIG. A cross-sectional view of a semiconductor device showing a step, FIG. 2D is a cross-sectional view of a semiconductor device showing a step of removing the remaining photoresist layer shown in FIG. 2C, and FIG. 2E is a semiconductor showing a step of removing a residual nitride film shown in FIG. 2D. Cross section of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920007707A KR950009803B1 (en) | 1992-05-07 | 1992-05-07 | Patterning method of tft |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920007707A KR950009803B1 (en) | 1992-05-07 | 1992-05-07 | Patterning method of tft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930024183A true KR930024183A (en) | 1993-12-22 |
| KR950009803B1 KR950009803B1 (en) | 1995-08-28 |
Family
ID=19332792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920007707A KR950009803B1 (en) | 1992-05-07 | 1992-05-07 | Patterning method of tft |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950009803B1 (en) |
-
1992
- 1992-05-07 KR KR1019920007707A patent/KR950009803B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950009803B1 (en) | 1995-08-28 |
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| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20040719 Year of fee payment: 10 |
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