KR930023826A - Parity memory control circuit - Google Patents

Parity memory control circuit Download PDF

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Publication number
KR930023826A
KR930023826A KR1019920007456A KR920007456A KR930023826A KR 930023826 A KR930023826 A KR 930023826A KR 1019920007456 A KR1019920007456 A KR 1019920007456A KR 920007456 A KR920007456 A KR 920007456A KR 930023826 A KR930023826 A KR 930023826A
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KR
South Korea
Prior art keywords
parity
data
memory
control circuit
parity memory
Prior art date
Application number
KR1019920007456A
Other languages
Korean (ko)
Inventor
이희
정재훈
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Publication of KR930023826A publication Critical patent/KR930023826A/en

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Abstract

이 발명에 의한 패리티 메모리 제어회로는, 메인 메모리의 구성에 있어서, 패리티 메모리를 첵크하는 프로그램과 첵크하지 않는 프로그램이 저장된 EPROM 및 콤퓨터 제작자(시스템 메이커)의 선택에 의해 패리티 비트를 검사하거나 검사하지 않도록 하는 패리티 오류 및 금지부를 구비하여 패리티 메모리가 필요없는 콤퓨터에서는 패리티 메모리를 사용하지 않음으로써 저가의 콤퓨터 제작이 가능하고 시스템 보드가 간단해지며 사용자에게 선택의 폭을 넓혀 준다.In the parity memory control circuit according to the present invention, in the configuration of the main memory, the parity bit is not checked or checked by the selection of the EPROM and the computer manufacturer (system maker) storing the program that checks the parity memory and the program that does not check the parity memory. By using parity errors and prohibitions, computers that do not require parity memory do not use parity memory, making it possible to manufacture low-cost computers, simplifying system boards, and giving users more choice.

Description

패리티 메모리 제어회로Parity memory control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명에 따른 패리티 메모리가 없는 메인 메모리의 구성도, 제3도는 이 발명에 따른 패리티 메모리 제어회로에 대한 블럭도이다.2 is a block diagram of a main memory without a parity memory according to the present invention, and FIG. 3 is a block diagram of a parity memory control circuit according to the present invention.

Claims (2)

중앙처리장치로부터 데이타 메모리 데이타를 라이트하기 위한 버퍼와, 상기 데이타 메모리로부터 중앙처리장치로 데이타를 리드하기 위한 버퍼 및 데이타 리드 래치부와, 데이타를 라이트할 경우 패리티 비트를 발생시켜 패리티 메모리에 저장하고 데이타를 리드할 경우 리드하는 데이타의 패리티를 검사하고 저장된 패리티 비트와 비교하기 위한 패리티 비트 발생 및 비교부로 구성된 데이타 및 패리티 메모리회로에 있어서, 상기 패리티 비트 발생 및 비교부에 연결되어 패리티 메모리를 사용할 경우는 상기 패리티 비트 발생 및 비교부로부터 패리티 비교 신호를 입력받아 패리티 에러 여부를 출력하고, 패리티 메모리를 사용하지 않을 경우는 무조건 패리티 일치신호를 출력하도록 한 패리티 오류 및 금지부(30)가 구비된 패리티 메모리 제어회로.A buffer for writing data memory data from the central processing unit, a buffer for reading data from the data memory to the central processing unit, and a data read latch unit, and a parity bit for generating data and storing the data in the parity memory; A data and parity memory circuit comprising a parity bit generation and comparison unit for checking parity of data to be read when the data is read and comparing the stored parity bits with each other, and using the parity memory connected to the parity bit generation and comparison unit. Parity error and prohibition unit 30 is provided to receive a parity comparison signal from the parity bit generation and comparison unit to output a parity error, and to output a parity matching signal when the parity memory is not used. Memory control circuit. 제1항에 있어서, 상기 메인 메모리는 한 뱅크당 16개의 데이타 메모리로 구성된 패리티 메모리의 제어회로.The control circuit of claim 1, wherein the main memory comprises 16 data memories per bank. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920007456A 1992-05-01 Parity memory control circuit KR930023826A (en)

Publications (1)

Publication Number Publication Date
KR930023826A true KR930023826A (en) 1993-12-21

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012086914A1 (en) * 2010-12-22 2012-06-28 (주)케이티 Method for recovering errors from a plurality of error replicas and storage system using same
US8495013B2 (en) 2010-12-24 2013-07-23 Kt Corporation Distributed storage system and method for storing objects based on locations
US8849756B2 (en) 2011-04-13 2014-09-30 Kt Corporation Selecting data nodes in distributed storage system
US9052962B2 (en) 2011-03-31 2015-06-09 Kt Corporation Distributed storage of data in a cloud storage system
US9158460B2 (en) 2011-04-25 2015-10-13 Kt Corporation Selecting data nodes using multiple storage policies in cloud storage system
US9888062B2 (en) 2010-12-24 2018-02-06 Kt Corporation Distributed storage system including a plurality of proxy servers and method for managing objects

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012086914A1 (en) * 2010-12-22 2012-06-28 (주)케이티 Method for recovering errors from a plurality of error replicas and storage system using same
US8495013B2 (en) 2010-12-24 2013-07-23 Kt Corporation Distributed storage system and method for storing objects based on locations
US9888062B2 (en) 2010-12-24 2018-02-06 Kt Corporation Distributed storage system including a plurality of proxy servers and method for managing objects
US9052962B2 (en) 2011-03-31 2015-06-09 Kt Corporation Distributed storage of data in a cloud storage system
US8849756B2 (en) 2011-04-13 2014-09-30 Kt Corporation Selecting data nodes in distributed storage system
US9158460B2 (en) 2011-04-25 2015-10-13 Kt Corporation Selecting data nodes using multiple storage policies in cloud storage system

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