KR930018698A - Semiconductor chip package and module package using same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package and a module chip using the same. The present invention relates to a first package in which a connection part is formed and wiring patterns are formed in a module package that can be mounted without increasing soldering when mounting the semiconductor chip package. The semiconductor chip is mounted, and the semiconductor chip package molded by the COB method is mounted by vertically inserting the first connection terminals formed in the connection part into the slots formed in the second substrate, and at the same time, it is electrically connected with the wiring patterns of the second substrate. By connecting to the slots of the second substrate to connect the first connection terminal and the wiring pattern of the module substrate, there is no need for a separate soldering process, and also the semiconductor chip package in the slots without a hole in the second substrate It can mount by this and can improve a mounting density.

Description

Semiconductor chip package and module package using same

Since this is an open matter, no full text was included.

1 is a plan view showing an embodiment of a semiconductor chip package according to the present invention.

2 (a) and (b) are plan views showing temporary examples of the upper and lower surfaces of the first substrate of FIG.

3A and 3B are plan views showing other embodiments of the upper and lower surfaces of the first substrate of FIG.

Claims (15)

A semiconductor chip package vertically mounted, comprising: a semiconductor chip having a plurality of bonding pads, a substrate on which the semiconductor chip is mounted and having a connection portion; a plurality of wiring patterns formed on the substrate; A semiconductor chip package including a plurality of connection terminals connected to upper and lower portions, conductive lines connecting wiring patterns and bonding pads on the upper surface of the substrate, and a resin formed on the upper surface of the substrate to mold the semiconductor chip and the conductive lines. The semiconductor chip package of claim 1, wherein the wiring patterns are formed around the semiconductor chip on an upper surface of the substrate and connected to the connection terminals at a lower surface thereof. The semiconductor chip package of claim 1, wherein the through holes are formed in the wiring patterns outside the semiconductor chip region. The semiconductor chip package of claim 3, wherein a wiring pattern is formed in the through holes. The semiconductor chip package of claim 1, wherein the wiring patterns are formed on an upper surface of the substrate. The semiconductor chip package of claim 5, wherein the semiconductor chip is adhered to the substrate with an insulating adhesive tape. In a semiconductor chip capacitor vertically mounted, a semiconductor chip having a plurality of bonding pads, the semiconductor chip is mounted on the upper and lower surfaces, respectively, and mounted on the upper and lower surfaces, respectively, having a connection portion, and formed on the substrate A plurality of wiring patterns, a plurality of connection terminals connected to the wiring patterns and connected to the upper and lower portions of the connection part, the wires connecting the wiring patterns and the bonding pads, the semiconductor chip and the wires are molded. A semiconductor chip package comprising resins as possible. The semiconductor chip package of claim 7, wherein the semiconductor chip package has the same wiring pattern on upper and lower surfaces of the substrate. The semiconductor chip package of claim 8, wherein the semiconductor chips are adhered to the upper and lower surfaces of the substrate by an insulating adhesive tape. In the module package, a plurality of semiconductor chip packages mounted on a first substrate having a connecting portion formed with a first contact terminal on the upper and lower surfaces and molded with resin by a COB method, and the semiconductor chip packages A module package having a second substrate having slots for connecting the connection parts to be perpendicular to each other and wiring patterns, and second connecting terminals electrically connected to the first connection terminals by the wiring patterns. The module package of claim 10, wherein the semiconductor chip package is formed on an upper surface of the first substrate. The module package of claim 10, wherein the semiconductor chip package is formed on upper and lower surfaces of the first substrate. The module package of claim 10, wherein the first connection terminals and the wiring patterns are electrically connected to each other by inserting the semiconductor chip packages into slots. The module package of claim 10, wherein the slots are formed at equal intervals. The module package of claim 13, wherein a width of the slots is equal to a thickness of the first substrate. ※ Note: The disclosure is based on the initial application.