KR930017373A

KR930017373A - Message transfer interface module of electronic exchange

Info

Publication number: KR930017373A
Application number: KR1019920001565A
Authority: KR
Inventors: 윤성철
Original assignee: 정장호; 금성정보통신 주식회사
Priority date: 1992-01-31
Filing date: 1992-01-31
Publication date: 1993-08-30
Also published as: KR970003136B1

Abstract

본 발명은 전자교환기의 베세지 전송 인터페이스 모듈에 관한 것으로 이것은 특히 인터럽트 신호를 이용하여 다수의 로칼 프로세서간 메세지 전달을 기능적으로분리시켜 데이터 송수신 속도를 빠르게 한 것이다.The present invention relates to a message transfer interface module of an electronic exchange, and in particular, it is possible to speed up data transmission and reception by functionally separating message transfer between multiple local processors using an interrupt signal.

종래의 로칼 프로세서간 메세지 전달 모듈은 각각의 UART를 갖고 있으면서 그 UART를 통해 직렬전송 방식으로 로칼 프로세서간 통신이 이루어지므로 메인 프로세서가 메세지를 처리시 충분한 시간간격으로 데이터가 수신되지 않을 때는 데이타가 유실되는 경우가 발생되었다.In the conventional local processor message transfer module, each UART has its own UART and the local processor communicates through the serial transmission method through the UART. When the main processor does not receive data at sufficient time intervals when processing a message, data is lost. A case was made.

본 발명에서는 상기의 문제점을 개선하기 위해 전자교환기 내의 각 로칼 프로세서간 정보 및 데이터 송수신을 위한 메세지 전달 인터페이스 모듈을 기능적으로 분리시켜 프로세서간의 병렬통신 통로를 통해 메세지 전달이 이루어지게 한 것이다.In the present invention, in order to improve the above problems, the message transfer interface module for transmitting and receiving information and data between local processors in the electronic exchange is functionally separated so that the message is transmitted through the parallel communication path between the processors.

Description

Message transfer interface module of electronic exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 메세지 전달모듈 블럭도, 제3도는 제2도의 메세지 전송 인터페이스 모듈(PBIM) 상세회로도.2 is a block diagram of a message transfer module of the present invention, and FIG. 3 is a detailed circuit diagram of a message transfer interface module (PBIM) of FIG.

Claims

A memory addressing circuit for specifying a memory address by selecting a clock and an address, a memory data connecting circuit for selecting a message of a main processor and a message of a local processor, and connecting the data of the memory with the data; The enable signal generator 70 for determining the selection time and the local processor check unit 80 for determining the number of the local processor are configured to functionally separate the message transmission interface module. Message transfer interface module.

The memory addressing circuit (1) according to claim 1 comprises a clock generator (10) for generating a clock having various cycles synchronized with 2 (MHz), a main processor (MP), and a local processor (LP). And an address selector (20) for determining an address and a memory (30) for storing interprocessor communication messages.

The memory data connection circuit (b) of claim 1 includes an interrupt generator 40 for generating an interrupt for the main processor MP to set a time for sending and receiving a message to the main processor MP. An electronic exchanger comprising: a memory buffer unit 50 for allowing the processor MP to read memory messages; and a data selector 60 for selecting data of the main processor MP and the local processor LP. Message transfer interface module.

※ Note: The disclosure is based on the initial application.