KR0121116Y1 - Message transceiving system among multi-processor - Google Patents

Abstract

The present invention relates to a message transmission and reception device between multiple processors, and to a message transmission and reception device between multiple processors to prevent the loss of messages during message transmission and reception and to improve system performance.

The present invention manages the transmission / reception of messages without loss, and the processor performs the message input / output operation only when there is a message in the message delivery unit, thereby improving system performance by increasing the data processing efficiency of the processor.

Description

Message Transceiver between Multiple Processors

1 is a block diagram of a conventional multi-processor message transceiver

2 is a block diagram of a multi-processor message transceiver according to the present invention

3 is an internal block diagram of the message transfer unit shown in FIG.

* Explanation of symbols for main parts of the drawings

100a, 100b: Processor 120a, 120b: Control circuit

110a, 110b: Message delivery section 111: Transmission memory section

112: receiving memory unit 113: sending infointer

114: Outgoing pointer 100: Reception infointer

116: reception out pointer 117: timing control circuit

118: message header check section 119: memory section

The present invention relates to a multi-processor message transceiver, and more particularly to a multi-processor message transceiver to improve the system performance while preventing the loss of the transmission and reception messages.

A conventional message transmitting and receiving device will be described with reference to FIG.

As can be seen in Figure 1, a conventional message delivery device is composed of a module (A) and a module (B). The module A transmits a message to the buffer 11a and the processor 10a for sending and receiving messages, and sends a message from the processor 10a to the module B and sends the message received from the module B to the processor 10a. A buffer 11a outputted to the side, and a control circuit 12a for controlling message transmission / reception operations of the processor 10a and the buffer 11a. Module (B) transmits a message from processor (10b) to processor (10b) and a processor (10b), and sends a message from processor (10b) to module (A). A buffer 11b for outputting to the "

When the processor 10a of the module A sends a message to the module B side through the buffer 11a under the control of the control circuit 12a, the message from the module A is received in the buffer 11b and the buffer 11b transfers the received message to the processor 10b under the control of the control circuit 12b. Similarly, if the processor 10b in the module B sends a message to the module A side through the buffer 11b under the control of the control circuit 12b, the message from the module B is received in the buffer 11b. The buffer 11a is transferred to the processor 10a under the control of the control circuit 12a.

In the conventional interprocessor message transmitting / receiving apparatus, when the message is stored in the buffers 11a and 11b, the processor 10a and 10b cannot confirm whether or not the message has been read in the processors 11a and 11b. If the amount is large, the message may be lost, and the processor 10a and 10b should check the contents of all buffers 11a and 11b regardless of the amount of messages sent and received. There was a problem that lowers.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an apparatus for transmitting and receiving messages between processors to prevent loss of transmission and reception messages and to improve system performance.

A feature of the present invention for achieving this object is a message delivery unit for transmitting a message supplied from a processor to another module side and supplying a message received from another module to the processor side, and a message transmission and reception operation of the processor and the message delivery unit. A message transmission and reception apparatus between a plurality of processors having a control circuit for controlling a message, the message transfer unit comprising: a message header check unit for receiving a message to be received by the user by checking a head portion of a message supplied from another module, and the message A memory unit for outputting a message supplied from a header check unit to the processor side, transmitting a message supplied from the processor to another module side, and recording information on the amount of messages input and output between the processor and the other module, and supplied from the control circuit; Article Depending on the signals to a timing control unit for controlling parts of the memory.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The multi-processor message transmission and reception device according to the present invention is composed of a module (A) and a module (B) as shown in FIG.

The module A outputs a message supplied from the processor 100a, a processor 100a for transmitting and receiving a message, a message supplied from the processor 100a to the module B, and outputs a message supplied from the module B. The message transmission unit 110a outputs to the processor 100a side, and the control circuit 120b for controlling message transmission / reception operations of the processor 100a and the message transmission unit 100a.

The module B outputs a message supplied from the processor 100b, a processor 100b for transmitting and receiving a message, a message supplied from the processor 100b to the module A, and outputs a message supplied from the module A. The message transfer unit 110b outputs to the processor 100b side, and the control circuit 120b for controlling the message transmission and reception operations of the processor 100b and the message transfer unit 110b.

3 is an internal block diagram of each of the message transfer units 110a and 110b shown in FIG. As shown in FIG. 3, the message transfer units 110a and 110b control timings of input and output of the transmit and receive memory units 111 and 112 under the control of the control circuit 120a or 120b. And a message header check unit 118 that checks the head portion (address) of a message input from an external module to check whether it is a message to be received and outputs only the message to be received to the memory unit 119. Outputting the message supplied from the header check unit 118 to the processor 100a or 100b under the control of the timing control circuit 117 and transmitting the message supplied from the processor 100a or 100b to the other module side. The memory unit 119 is provided.

The memory unit 119 is configured to receive the message supplied from the message header check unit 118 to the processor 100a or 100b side under the control of the timing control circuit 117, and the reception memory unit 112 A receiving pointer 115 for recording information on the amount of messages input to the message 112, a receiving pointer 116, a processor 100a or 100b for recording information on the amount of messages output from the receiving memory section 112; ), A transmission memory unit 111 for transmitting a message supplied from the message to the other message transmission unit side, a transmission pointer 113 for recording information on the amount of messages input to the transmission memory unit 111, and a transmission memory unit 111. And a transmission pointer 114 for recording information on the amount of messages output from the < RTI ID = 0.0 >

When a message is supplied from the message header checking unit 118 to the receiving memory 112 side, information on the supplied message amount is recorded in the receiving pointer 115, and the message of the receiving memory unit 112 is stored in the processor 100a or ( When output to the 100b) side, the information on the output message amount is recorded in the reception out pointer 116. The processor 100a or 100b reads the information recorded in the reception pointer 115 and the reception out pointer 116 to grasp the amount of messages input and output to the reception memory unit 112, so that the message of the reception memory unit 112 is received. It can be managed so as not to be lost.

When a message is supplied from the processor 100a or 100b to the transmission memory section 111, information on the supplied message amount is recorded in the transmission pointer 113, and the message of the transmission memory section 111 is stored on the other side. When transmitted to the message delivery section of the module, information on the amount of messages sent is recorded in the transmission pointer 114. The processor 100a or 100b reads the information recorded in the transmission infointer 113 and the transmission pointer 114 and grasps the amount of messages inputted and outputted to the transmission memory 111 so that the transmission memory 111 can be read. You can manage the messages so that they are not lost.

On the other hand, the processor (100a, 100b) is a transmission memory unit 111 and a receiving memory unit 112 through the transmission infointer 113, the transmission out pointer 114, the reception infointer 115 and the reception out pointer 116. By checking the amount of messages present in the C), it is possible to improve system performance by performing message input / output operations only when there are messages in the corresponding transmission / reception memory units 111 and 112.

As described above, the present invention manages transmission and reception messages so that they are not lost, and the processor performs message input / output operations only when there are messages in the message delivery unit, thereby improving system performance by increasing the data processing efficiency of the processor.

Claims (2)

A message transfer unit 100a / 100b for transmitting a message supplied from the processor 100a / 100b to another module side and supplying a message received from another module to the processor 100a / 100b side, and the processor 100a / 100b. And a control circuit (120a / 120b) for controlling the message transmission and reception operation of the message transmission unit (100a / 100b), the message transmission unit (100a / 100b), from the other module A message header checker 118 for checking a head of a supplied message and receiving a message to be received by the user, and outputting a message supplied from the message header checker 118 to the processor 100a / 100b; A memo for transmitting a message supplied from the processor 100a / 100b to another module and recording information on the amount of messages input and output between the processor 100a / 100b and another module. Section 119 and the control circuit unit transmitting and receiving messages between the multiple processors comprising the timing control section 117 for controlling the memory unit 119 according to a control signal supplied from (120a / 120b). The receiving memory unit of claim 1, wherein the memory unit 119 outputs a message supplied from the message header checker 118 to the processor 100a / 100b under the control of the timing control circuit 117. (112), a reception pointer (115) for recording information on the amount of messages input to the reception memory section (112), and a reception out for recording information on the amount of messages output from the reception memory section (112). A pointer 116, a transmission memory section 111 for transmitting a message supplied from the processor 100a / 100b to another module side under the control of the timing control circuit 117, and the transmission memory section 111; And a transmission pointer 113 for recording information on the amount of messages to be input, and a transmission pointer 114 for recording information on the amount of messages output from the transmission memory section 111. Processor Inter-message transceiver.