JPS58105344A - Buffer memory controlling system - Google Patents

Abstract

PURPOSE:To perform assured buffering of data with reduced memory capacity, by dividing a shared memory into plural numbered memory blocks and controlling the using conditions of the divided memory blocks with plural register memories which are provided separately. CONSTITUTION:A processor 1 is started and divides the storage region of a shared memory 2 into plural memory blocks. A serial numbers are added to each divided memory block, and these block numbers are registered to an idle block register memory 3. Wen a serial-parallel converting part 7 receives data from another communication controller, the converter 7 extracts the idle block number out of the memory 3 and stores successively the received data underwent a serial-parallel conversion to the memory blocks in the memory 2 which corresponds to the block number. Then the numbers of the used blocks are registered to a received data storing block register memory 6 at a time point when a series of data reception is over.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory management system, and is particularly suitable for application to a transmitting/receiving buffer memory in a communication control device of a data highway system that transmits and receives data to and from an unspecified number of parties at high speed and asynchronously. This relates to a buffer memory management method.

Generally, in data transmission, when data is to be sent or received, it is stored in the data tube-1 sending/receiving buffer memory. In this case, the management method for the transmitting/receiving buffer memory is, taking reception as an example, determining the area where the next received data will be stored after the previous received data has been stored, and determining the area where the next received data is stored. The method of storing the next received data in the free area following the area is the most efficient in memory usage. Therefore, this method is generally adopted, but in this method, the storage location of received data is determined every time t-1 data reception is completed, so while data is being received with one party, data transmission from another party is not possible. However, in communications in data highway systems where data is sent simultaneously from an unspecified number of parties at high speed and asynchronously, it is possible to miss received data. It will end up being put away. In such a case, secure enough memory area in advance to store the previously received data,
The next received data can be stored in other free areas, but if the length of the received data is undefined, it is necessary to reserve free space for the longest amount of data, so the required transmit/receive buffer memory capacity is The disadvantage is that the memory usage increases significantly and memory usage efficiency decreases.

The present invention was made in order to improve these conventional drawbacks, and its purpose is to improve data transmission as much as possible even when data is sent asynchronously, rapidly, and intensively from multiple parties. To provide a buffer memory management method capable of reliably buffering data with a small memory capacity.

Examples will be described in detail below.

The figure is a block diagram of the main parts of a communication control device in a data highway system that implements an embodiment of the present invention.
1 is a processing device (first processing device) that processes data generated by the own communication control device and data generated by other communication control devices; 8 is a shared memory used as a transmission/reception buffer and a human output buffer; As will be described later, the storage area line is divided and used in units of memory blocks each having a fixed length.

Further, 3 is a free block registration memory (first registration memory) for registering the numbers of usable free blocks among the plurality of memory blocks in the shared memory 2, and 4 is in the shared memory block in which the transmission data is stored. 5 is a transmission data storage block registration memory (20th register memory) for registering the number of the memory block in the shared memory; 6 is a reception data storage block registration memory (registration memory of Series 4) for registering the number of the memory block in the shared memory in which received data is stored; transmission 1 of the 'rFi self-communication control device;
゛A serial-to-parallel converter (parallel converter) that converts data from parallel to serial and sends it to other communication control devices via communication circuit @S, converts data from other communication control devices from serial to parallel, and takes it into its own communication control device. 10 processing equipment) □.

Note that the memories 3 to 6 are first-in, first-out (Flrat in, Flrmt out) memories that can retrieve the contents that have been set (stored) first, and have a capacity that can store multiple block numbers. have.

In the figure, when the processing device 1 is activated, it divides the storage area of the shared memory 2 into a plurality of memory blocks, assigns a series number to each block, and registers the block number in the free block register memory 3. do.

The storage area size of the above memory blocks is all the same! −
Although the size of each memory block may be different or different, the size of each memory block is not changed and is set to a fixed length.

When transmission data is generated within its own communication control device, the processing device 1 extracts an empty block number from the empty block memory 3, stores the transmission data in the memory block of that number in the shared memory 2, and then transfers the data to that block. The number is registered in the transmission data storage block registration memo 174. When a new block number is registered in the memory 4, the serial/parallel converter 7 extracts the block number from the transmission data storage block registration memory 4 and converts the contents of the memory block in the shared memory 2 corresponding to that number. Communication time 11B by serial-parallel conversion
to other communication control devices via. After the transmission is completed, the number of the block that has been transmitted is registered in the transmission completed block registration memory 5.

When the block number is registered in the memory 5, the processing device IK
The processing device 1, which is configured to be interrupted, takes out a block number from the memory 5, registers the block number in the free block registration system 3, and makes the block usable.

When a plurality of block numbers are stored in the memory 5, the block numbers are taken out from the memory 5 one after another and set in the memory 3. Note that this memory number can be retrieved at will.

On the other hand, when the serial-to-parallel converter 7 receives data from another communication control device, the serial-to-parallel converter 7 retrieves an empty block number from the empty block registration memory 3 and stores data in the shared memory 2 corresponding to the block number. The serial-to-parallel converted received data is stored one after another in the memory block. Then, when a series of data reception is completed, the number of the block used is registered in the received data storage block registration memory 6. In this case, when a series of data is received one after another, the free block numbers are taken out one after another from the free block registration memory 3, and the number of the block used each time reception is completed is stored in the received data storage block registration memory. Register on 6.

When the block number is registered in the memory 6, the processing device IK
The processing device is configured to receive an interrupt.
A block number is extracted from the received data storage block registration memory 6, and the shared memory 2 corresponding to the block number is retrieved.
Process data in memory blocks within. Then, when the data processing is completed, the number of the processed block is registered in the free block registration memory 3.

As described above, in the method of this embodiment, the shared memory is divided into a plurality of memory blocks with serial numbers, and the block numbers are stored in the free block registration memory 3Kiifi. Depending on the method, the block number is extracted and the memory block of the shared memory mentioned above corresponding to that number is used.If one memory block is not enough, The remaining memory blocks can be used one after another, and there is no need to reserve the maximum storage area for data in advance even if data is input from multiple parties, improving memory usage efficiency. becomes possible. Therefore, even in asynchronous, high-speed, intensive data reception, reliable data buffering is possible with the minimum memory capacity. In particular, in the case of this embodiment, the shared memory 2 is also used as a transmission buffer, etc., so that the memory usage efficiency is further increased. As a result of using 7 first-in, first-out memories in memories 3 to 6, the order of received data can be easily managed, and there is no problem even if the order of reception is important. Further, it becomes possible to efficiently transmit and receive various data having different data lengths.

In the above embodiments, the method of the present invention is applied to transmitting/receiving buffering within a communication control device, but the method of the present invention is not limited to this, and can be applied to various other types of data buffering. It's something you get. For example, it is possible to use a multiprocessor system in which a plurality of processors share a memory.

As can be seen from the above description, according to the present invention, a shared memory is divided into a plurality of memory blocks with serial numbers, and each memory block is managed by separately setting and registering the usage status of each memory block. It should be able to be used dynamically for sending/receiving buffers, input/output buffers, etc., and it should be possible to use as little memory as possible even when data is sent asynchronously and at high speed from multiple parties. It has the advantage of being able to reliably buffer data with its capacity.

[Brief explanation of drawings]

The figure is a block diagram of a main part of a communication control device that implements an embodiment of the present invention. 1 is a processing unit, 2 is a shared memory, 3 is an empty block registration memory, 4 is a transmission data storage block registration memory, 5 is a transmission completion block registration memory, 6 is a reception data storage block registration memory, 7 is a serial/parallel The conversion block 8 is a communication line. Patent Applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney Hisashi Tamamushi Gobe

Claims (1)

[Claims] In a buffer memory management method for butt-springing first data sent from a first processing device to a processing device @g and second data sent from the second processing device to the first processing device, a shared memory in which the storage area is composed of a plurality of fixed-length memory blocks assigned a series of numbers; a first registration memo for registering the numbers of free memory blocks in the shared memory; a second registration memory for registering the number of the memory block in the shared memory that has stored the data I11; and a second registration memory for registering the number of the memory block in the shared memory that has stored the data I11 to the second processing device; A third registration memory for registering a number and a fourth registration memory for registering a number of a memory block in the shared memory storing the second data, the first data transmission line to the processing device; the first processing device retrieves the static block number from the free block registration memory and transmits the data to the memory block of that number in the shared memory; The data is stored and the block number is registered in the second registration memory, and the second processing device retrieves the block number registered in the second registration memory and stores the block number in the shared memory. reads the first data stored in the memory block and registers the block number in the third registration memory, and the first processing device reads the block number registered in the third registration memory. when the second data is sent from the second processing device to the first processing device; A processing device extracts an empty block number from the first registration memory, stores the second data in a memory block of that number in the shared memory, and registers the block number in the fourth registration memory. Returning, the first processing device is Mukuro No. 40 No. 17 K
The registered block number is extracted and the 1[[
A buffer memory management system characterized in that the data is read and processed, and the block number is registered in the first registration memory after the processing is completed.