KR930017345A

KR930017345A - Serial data receiver

Info

Publication number: KR930017345A
Application number: KR1019920000325A
Authority: KR
Inventors: 슝이치 나가모토; 타케시 무라마쯔; 테루에 마쯔무라
Original assignee: 다니이 아끼오; 마쯔시다덴기산교 가부시기가이샤
Priority date: 1992-01-13
Filing date: 1992-01-13
Publication date: 1993-08-30
Also published as: KR960000544B1

Abstract

본 발명은 매우 열악한 SN비의 직렬데이터의 수신처리를 간단한 구성으로 염가에 실현하는 것을 목적으로 한다. 직렬데이터의 1비트길이를 몇개의 블록으로 분할하여 생각하고, 이 블록마다 마이크로컴퓨터에 내장되는 시프트레지스터를 사용해서 고속으로 다점샘플링입력한다. 그 데이터를 일시적으로 축적해두고, 동일번호의 블록 몇비트분정도를 가산하면 노이즈성분은 소거되어서 원래의 신호성분만 남는다. 이 중첩처리 수신방식에 의해, 비트동기용 프리앰블신호의 수신위상을 명확하게 하고, 비트동기를 확립한다. 다음에 이 구한 수신타밍을 기준으로 데이터신호를 다점샘플링입력하고 그 데이터의 "1" 또는 "0"의 수의 비율에 따라서 그 비트의 논리치를 판정한다. 또 바이패스즈부호의 전반부와 후반부의 반전대칭성을 이용해서 보다 효과적으로 고정밀도의 비트동기확립 방법과 비트논리 판정방법을 실현한 직렬 데이터수신장치를 제공한다.An object of the present invention is to realize an inexpensive process of receiving serial data having a very poor SN ratio with a simple configuration. The length of one bit of serial data is divided into several blocks, and each block is input at high speed using a shift register built in a microcomputer. If the data is temporarily accumulated and a few bits of the same number are added, the noise component is erased, leaving only the original signal component. By the superposition processing reception method, the reception phase of the bit synchronization preamble signal is made clear and bit synchronization is established. Next, multi-point sampling is input to the data signal on the basis of the obtained reception timing, and the logical value of the bit is determined according to the ratio of the number of "1" or "0" of the data. In addition, a serial data receiving apparatus that realizes a high accuracy bit synchronization method and a bit logic determination method more effectively by using the inverse symmetry of the first half and the second half of the bypass code is provided.

Description

Serial data receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 실시예의 직렬데이터 수신장치의 블록구성도, 제4도는 동 장치의 일부동작타이밍도, 제5도는 동 장치의 다른 일부동작타이밍도, 제7도는 동 장치의 다른 일부동작타이밍도, 제8a도는 동 장치의 일부 동작 순서도, 제8b도는 동 장치의 다른 일부동작순서도, 제8c도는 동 장치의 다른 일부동작순서도.1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention, FIG. 4 is a partial motion timing diagram of the apparatus, FIG. 5 is another partial motion timing diagram of the apparatus, and FIG. 7 is a partial motion timing diagram of the apparatus. Fig. 8A is a flowchart of a part of the apparatus, Fig. 8B is a flowchart of another portion of the apparatus, and Fig. 8C is a flowchart of another portion of the apparatus.

Claims

Compaction sampling input means for inputting multi-point sampling data for each block by setting a small section divided by N (N is a natural number) into one block of the bit synchronization preamble signal transmitted as a serial data signal as a data input unit And block logic determining means for determining a logical value in the block as "1", "0", or "negative" based on the sampling input data obtained by this multi-point sampling input means. Phase relationship between the bit synchronization preamble signal inputted on the basis of the permutation pattern of each block logic value from block No, 1 to block No, N obtained by And a bit synchronization establishing means for finding a bit synchronization and establishing bit synchronization.

The method of claim 1, wherein one bit length of the bit synchronization preamble signal is divided into an even number N (N = 2n, n = 1,2,3,4,5 ...) to form one block. Serial data receiver.

3. The block logic determining means according to claim 2, wherein the block logic determining means comprises a first (1) obtained by the multipoint sampling input means. i On the basis of the sampling input data in the block (integer of n) and the sampling input data in the (i + n) th block, the logical decision is made in the i th block. Block No. obtained by the block logic determination means. Block No. at 1 On the basis of the permutation pattern of the logical values of each block up to n, the input bit synchronization preamble signal and the block no. A serial data receiving apparatus characterized by finding a phase relationship with an end point of 2n (starting point of block No. 1) and establishing bit synchronization.

The multi-point sampling input unit is configured to perform multi-point sampling input processing for each block over a plurality of bits of a bit synchronization preamble signal, and to simultaneously input sampling input data of the same block number in each bit. A block data calculating means for integrating is formed, and the block logic determination means is configured to perform logical determination of the block based on the block-by-block integration data obtained by the block data integration means.

A shift register for holding the serial data which has been serially transmitted, and a shift clock generator for generating a shift clock signal for giving a timing of data input and data shift to the shift register; A serial data receiver according to claim 1, wherein the half-bit time length of the serial data is shorter than the time divided by the number of shift registers.

The serial data receiving apparatus according to claim 1 or 5, further comprising a shift clock counter for outputting a shift input completion signal when the number of shift clock signals equal to the number of stages of the shift register is counted.

The input data logic determination according to claim 1 or 5, wherein the number of " 1 " (or " 0 ") in the input data induced in the shift register is calculated, and the logical determination of the input data is made based on the value. A serial data receiving apparatus comprising means.

6. The method according to claim 1 or 5, wherein when the input data is input as an address value in order to calculate the number of " 1 " (or " 0 ") in the input data held in the shift register, the input data is input. And a data conversion means having a data conversion table configuration in which the number of " 1 " (or " 0 ") to be configured is output.

Multi-point sampling input means for inputting multi-point sampling data into respective sections of the first half and the second half of each bit of serial data having a serial-coded by-pass code structure, and the multi-point sampling data input by the multi-point sampling input means. Data conversion means for calculating the number of " 1 " (or " 0 ") and the number of " 1 " (or " 0 ") in the first half and second half of the bit calculated by the data conversion means. A serial data receiving device comprising bit logic determination means for performing logic determination of bits.

10. The bit logic determination means according to claim 9, wherein the bit logic determining means includes the logic of the section in which the logic is clearer in the ratio of "1" and "0" in the first half or the second half of the bit constituted by the bypass code. A serial data receiving device comprising a configuration employing logic.

10. The bit logic determining means according to claim 9, wherein the bit logic determining means comprises a number of " 1 " (or " 0 ") of the first half of the bit constituted by the bypass code and a number of " 0 " (or " 1 ") of the second half. A serial data receiving device, characterized in that the logic is determined according to the sum.

※ Note: The disclosure is based on the initial application.