KR970056027A

KR970056027A - Reverse Interleaving Device for Personal Communication System

Info

Publication number: KR970056027A
Application number: KR1019950071018A
Authority: KR
Inventors: 곽재봉
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1995-12-30
Filing date: 1995-12-30
Publication date: 1997-07-31

Abstract

본 발명은 개인통신 시스템에 있어서 기지국과 단말기 간의 데이터 송수신기에 데이터를 인가받음에 있어 심도 19로 인터리빙된 228비트의 데이터를 역인터리빙하여 본래의 데이터를 복구할 수 있도록 된 개인통신 시스템용 역인터리빙장치에 관한 것으로서, 228비트의 데이터를 입력함과 더불어 소정의 클록신호에 따라 그 입력된 데이터를 직렬로 출력하는 데이터입력수단과, 상기 데이터입력수단에서 출력되는 데이터를 12비트의 비트단위로 입력하여 병렬로 출력하는 시프트레지스터, 상기 시프트레지스터의 각 비트출력을 순차로 19비트 입력하고, 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터시프트수단 및, 상기 데이터시프트수단으로부터 출력되는 병렬데이터를 로드한 후 소정의 클록신호에 따라 이를 직렬로 출력하는 데이터출력수단을 포함하여 구성된 것을 특징으로 한다.The present invention relates to a deinterleaving apparatus for a personal communication system, which is capable of recovering original data by deinterleaving data of 228 bits interleaved with a depth of 19 when receiving data from a data transceiver between a base station and a terminal in a personal communication system. The present invention relates to data input means for inputting 228 bits of data and outputting the input data serially in accordance with a predetermined clock signal, and inputting data output from the data input means in units of 12 bits. Shift registers output in parallel, 19-bit input of each bit output of the shift registers sequentially, data shift means for outputting them in parallel according to a predetermined clock signal, and parallel data output from the data shift means. The number of data outputs in series after the predetermined clock signal And it is characterized in that is configured including a.

Description

Reverse Interleaving Device for Personal Communication System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 개인통신 시스템의 전반적인 구성을 나타낸 시스템 구성도.1 is a system configuration diagram showing the overall configuration of a personal communication system.

제2도는 일반적인 인터리빙의 개요를 설명하기 위한 도면.2 is a diagram for explaining an outline of general interleaving.

Claims

Data input means for serially outputting 228 bits of data and outputting the input data serially according to a predetermined clock signal, and outputting the data output from the data input means in units of 12 bits and outputting them in parallel. A shift register, data shifting means for sequentially inputting 19 bits of each bit output of the shift register, and outputting them in parallel according to a predetermined clock signal; and loading a parallel data output from the data shifting means and then loading a predetermined clock. Reverse interleaving apparatus for a personal communication system, characterized in that it comprises a data output means for outputting it serially in accordance with the signal.

※ Note: The disclosure is based on the initial application.