KR970056028A

KR970056028A - Interleaving Device for Personal Communication System

Info

Publication number: KR970056028A
Application number: KR1019950071019A
Authority: KR
Inventors: 곽재봉
Original assignee: 유기범; 대우통신 주식회사
Priority date: 1995-12-30
Filing date: 1995-12-30
Publication date: 1997-07-31

Abstract

본 발명은 개인통신 시스템에 있어서 기지국과 단말기 간의 데이터 송수신기에 데이터를 인터리빙처리함에 있어 456비트의 데이터를 심도 8로 인터리빙하기 위한 개인통신 시스템용 인터리빙장치에 관한 것으로서, 456비트의 데이터를 입력함과 더불어 소정의 클록신호에 따라 그 입력된 데이터를 직렬로 출력하는 데이터입력수단과, 상기 데이터입력수단에서 출력되는 데이터를 8비트의 비트단위로 입력하여 병렬로 출력하는 시프트레지스터, 상기 시프트레지스터의 각 비트출력을 순차로 57비트 입력하고, 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터시프트수단 및, 상기 데이터시프트수단으로부터 출력되는 병렬데이터를 로드한 후 소정의 클록신호에 따라 이를 병렬로 출력하는 데이터출력수단을 포함하여 구성된 것을 특징으로 한다.The present invention relates to an interleaving apparatus for a personal communication system for interleaving data of 456 bits to a depth of 8 in interleaving data to a data transceiver between a base station and a terminal in a personal communication system. In addition, data input means for serially outputting the input data according to a predetermined clock signal, a shift register for inputting data output from the data input means in units of 8 bits and outputting in parallel, each of the shift registers. Data shifting means for sequentially inputting 57 bits of bit output and outputting them in parallel according to a predetermined clock signal, and loading parallel data outputted from the data shifting means and outputting them in parallel according to a predetermined clock signal. Characterized in that it comprises a data output means.

Description

Interleaving Device for Personal Communication System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 1실시예에 따른 개인통신 시스템용 인터리빙장치를 나타낸 회로구성도.3 is a circuit diagram showing an interleaving apparatus for a personal communication system according to an embodiment of the present invention.

Claims

Data input means for inputting 456 bits of data and serially outputting the input data according to a predetermined clock signal, and outputting the data output from the data input means in units of 8 bits and outputting in parallel A shift register, data shifting means for sequentially inputting 57 bits of each bit output of the shift register, and outputting them in parallel according to a predetermined clock signal, and loading a parallel data outputted from the data shifting means and then predetermined clock Interleaving device for a personal communication system, characterized in that it comprises a data output means for outputting it in parallel according to the signal.

※ Note: The disclosure is based on the initial application.