KR100775903B1 - Apparatus for restoring data for serial data rink - Google Patents

Abstract

The present invention relates to a data restoration apparatus for a serial data link, and provides a data restoration apparatus for a serial data link capable of restoring data at high speed. The present invention for this purpose is an oversampler for oversampling the input serial data three times the reference clock; A transition detector for detecting a data transition between adjacent bits of the oversampled serial data; A lock controller for controlling a lock to reorder the oversampled serial data according to the detected transition result; And a data estimator for rearranging the oversampled serial data according to the control of the lock controller and dividing the oversampled serial data into a window of a predetermined unit to estimate the serial data. With the above configuration, the present invention can recover data within the reference clock, and thus has an effect suitable for a high speed data link.

Serial Data, Link, Restoration Device, Transition Detection, Lock, Offer Sample, DVI

Description

Apparatus for restoring data for serial data rink}

1 is a block diagram showing the configuration of a data recovery apparatus for a serial data link according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing a detailed configuration of a part of FIG. 1. FIG.

3 is a view for explaining an example of data restoration according to an embodiment of the present invention;

4 is a data timing diagram of a serial data link.

Explanation of symbols on the main parts of the drawings

10: data recovery device 110: oversampler

120: transition detector 122: primary transition detector

124: second transition detection unit 130: lock controller

132: flag summer 134: partial summer

136: lock determining unit 140: data estimator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recovery apparatus for a serial data link. More particularly, the present invention relates to a data recovery apparatus for retrieving data transitions between adjacent bits of oversampled data and dividing the data into a predetermined unit to restore data at high speed based on the transitioned region. The present invention relates to a data recovery apparatus for a serial data link.

4 is a data timing diagram of a serial data link.

In general, as shown in FIG. 4, data transitions occur between the reference clocks due to jitter or data skew, which may act as a distortion of the data, and the data may be converted from the distortion. The data is resampled in the normal way, and the original data is restored based on the oversampled data.

However, as shown in FIG. 4, the data between the reference clocks maintains a constant value for most of the period in the normal case, whereas the data between the reference clocks has a different value for most of the period depending on the speed of the data. At this time, even if three times oversampling, only one of the three oversampling data maintains original data, which makes it difficult to restore the data normally by the conventional data restoration method.

Furthermore, conventional data recovery apparatus for serial data link controls the phase of the sampling clock by adjusting the phase of the phase controller to find the position of the symmetric data bits necessary for optimal data recovery, wherein the data bit rate is high. In this case, since the operating frequency of the phase controller or the like must be increased in order to restore data normally, there is a problem in that the operating frequency inside the restoration apparatus is relatively increased.

The present invention has been proposed to solve the above problems, and it is possible to retrieve data transitions between adjacent bits of oversampled data, and to recover data for a serial data link that can recover data at high speed using the data transitions. It is an object to provide a device.

The present invention for achieving the above object is an oversampler for oversampling the input serial data three times the reference clock; A transition detector for detecting a data transition between adjacent bits of the oversampled serial data; A lock controller for controlling a lock to reorder the oversampled serial data according to the detected transition result; And a data estimator for rearranging the oversampled serial data according to the control of the lock controller and dividing the oversampled serial data into a window of a predetermined unit to estimate the serial data.

Preferably, the transition detector divides the oversampled serial data into a window of a predetermined unit, and detects a data transition between adjacent bits, thereby generating a plurality of first transition change data and a first flag. ; The first transition change data may be divided into a window of a predetermined unit, and a plurality of secondary transition detection units generating second transition change data and a second flag using the first flag may be included.

Preferably, the lock controller performs an AND operation on the second transition change data and the second flag and outputs the AND operation result and the second transition change data; A partial adder for dividing each output of the plurality of flag adders into a first half, a middle half, and a second half to calculate respective sums; The lock determining unit may determine a lock position of the oversampled serial data according to the partial summation result.

And a first half adder for adding the second transition change data and the end result outputted first from each of the plurality of flag adders. A mid-sum adder for summing the second transition change data and the end result output second from each of the plurality of flag adders; And a second half adder configured to add the second transition change data and the end result, the third output from each of the plurality of flag adders.

Preferably, the window may be a 4-bit window.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a data recovery apparatus for a serial data link according to an embodiment of the present invention, Figure 2 is a block diagram schematically showing a detailed configuration of a portion of FIG.

The data recovery apparatus 10 includes an oversampler 110 for oversampling input serial data three times with respect to a reference clock, a transition detector 120 for detecting a data transition between adjacent bits of the oversampled serial data; A lock controller 130 for controlling the lock to reorder the oversampled serial data according to the detected transition result, and realigning the oversampled serial data according to the control of the lock controller 130, and by using a predetermined window It is composed of a data estimator 140 for dividing by and estimating the serial data.

The oversampler 110 samples the data at a faster rate than the reference clock provided to detect distortion of the signal due to jitter or data skew. This oversampling is used to detect data transitions that occur within the reference clock to normally recover data from distortion of the signal.

The transition detector 120 divides the serial data oversampled by the oversampler 110 into a window of a predetermined unit, and detects the data transition between adjacent bits to generate the first transition change data and the first flag. A plurality of secondary transitions for dividing the first transition detection unit 122a to c and the first transition change data into a window of a predetermined unit and generating first transition change data and a second flag using the first flag. It consists of the detection parts 124a-c.

The primary transition detection units 122a to c receive, for example, data oversampled by a 4-bit window. As shown in FIG. 2, the lower 1 bit of the oversampled previous data and the current oversampled are shown. A data transition between adjacent bits is detected based on three bits of data, and accordingly, the first transition change data and the first flag are output by the primary transition detection map shown in Table 1 below.

Oversampling Data Transition Data First transition change data (flag) 0000/1111 000 000 (0) 0001/1110 001 001 (0) 0010/1101 011 001 (1) 0011/1100 010 010 (0) 0100/1011 110 010 (1) 0101/1010 111 111 (0) 0110/1001 101 001 (1) 0111/1000 100 100 (0)

In Table 1, the oversampling data is oversampling data divided by a 4-bit window and input from the oversampler 110, and the transition data represents a data transition between adjacent bits of the oversampling data, and the first transition change data. Is the transitioned data, that is, when "1" is two or more, the transition data is changed for the variable operation of the lock controller 130 to be described later, and the first flag indicates this.
More specifically, when "1" is 1 or less in the transition data, for example, "000, 001, 010, 100", the transition data is generated as the first transition change data and the first flag is set to "0". Set to "." Also, in the transition data, when "1" is 2, for example, "011, 110, 101", the upper transition bit is inverted to "0" and changed to "001, 010, 001" so that the first transition is made. The change data is generated and the first flag is set to "1". On the other hand, when the transition data is "1" of 3, for example, "111", the first transition change data according to the original value is generated so that it is determined as a data error and is not reflected in the variable operation.

The secondary transition detection units 124a to c receive, for example, first transition change data by a 4-bit window. Referring to FIG. 2, the second transition detection unit 124b is referred to as the first stage. The lower two bits of the first transition change data and the first flag are input from the difference transition detection unit 122a, and the upper two bits of the first transition change data and the first flag are input from the current transition primary detection unit 122b. do.

Further, the secondary transition detection units 124a to c use the second transition change data according to the secondary transition detection maps of Tables 2 and 3 below based on the input 4-bit first transition change data and the first flag of the preceding stage. And a second flag.

Transition data Flag of flyer Second transition change data 0010 Don't care 001 0100 Don't care 010 1000 Don't care 100 1001 Don't care 100 0110 1/0 000/001 1010 1/0 000/001 And others Don't care 000

Transition Data 2nd flag 0101 ~ (Shear flag) and ~ (current flag) 0110 ~ (Shear flag) and ~ (current flag) 1010 ~ (Shear flag) and ~ (current flag) And others The current flag

In the above Table 2, the transition data is transition data inputted by two bits from the primary transition detection units 122a and b by being divided by a 4-bit window, and the front end flag is input from the primary transition detection unit 122a of the front end. The first flag, the second transition change data is for a variable operation used to determine the lock position in the lock controller 130.
In more detail, the upper three bits of the transition data are selected as the second transition change data, and the upper two bits or the lower two bits, that is, the primary transition detection unit 122b of the current stage or the primary transition detection unit 122a of the previous stage, are selected. In the case where the first change transition data, which is the output of N, is "11", as described above, the first change transition data is determined as a data error, and the second change transition data is set to "000" so that the data does not affect the variable operation.
In addition, as shown in FIG. 4, considering the case where the oversampled data for the minimum data does not sufficiently reflect the original data, the transition data is set separately when the transition data is "0101, 0110, 1010". do. For example, in the case of "0101", the second change data is set to "000" so as not to affect the variable operation, and only the second flag performs a separate operation. In the case of "0110, 1010", considering the first flag of the front end, if the first flag of the front end is "1", since the flag for variable operation has already been set, the second transition change data is "000". If the first flag is set to "0", the flag for variable operation is not set. Therefore, the upper 3 bits are set as the second transition change data. As shown above, the upper transition bit is inverted to "0" and changed to "001, 001".

In Table 3, the transition data indicates the same as the transition data in Table 2, and the flag of the front end is the first flag input from the primary transition detection unit 122a of the front end, and the flag of the rear end is the first transition detection unit of the rear end ( A first flag is input from 122b), and the second flag is used for the variable operation of the lock controller 130 together with the second transition change data.

Here, ~ () denotes a NOT operation, and and denotes an AND operation.
More specifically, in consideration of the high-speed data described above, the second operation is to be reflected in the variable operation only when the first flag is not set in both the first and second transition detectors 122a and 122b. Set the flag to "1" and set it to "0" because it is already reflected.
In other cases in which high-speed data is not taken into consideration, the second flag is set so that the first flag of the primary transition detection unit 122b at the rear end is reflected in the variable calculation.

The number of such primary transition detectors 122a to c and secondary transition detectors 124a to c is determined according to the characteristics of the serial data to be processed. For example, in the case of DVI (Digital Visual Interface) Since 10 bits are processed per reference clock of, the primary transition detection units 122a to c and the secondary transition detection units 124a to c may each consist of ten.

The lock controller 130 performs an AND operation on the second transition change data and the second flag output from the secondary transition detection unit 124, and outputs a plurality of flag summers that output the end operation result and the second transition change data ( 132a to c), and separate outputs of the plurality of flag summers into the first half, the middle half, and the second half to calculate the respective sums, and according to the sum result of the partial summers 134a-c. And a lock determination unit 136 for determining a lock position of the oversampled serial data.

The flag adders 132a to c are used to assign an additional value by the second flag before adding the second transition data for each part. Referring to FIG. The lower 1 bit of the second flag and the second transition change data are input from the secondary transition detection unit 124a, and the upper two bits of the second transition change data are input from the secondary transition detection unit 124a of the current stage.

In addition, the flag summers 132a-c perform AND operation on the second transition change data and the second flag, which results in a bit whose value is "1" among the second transition change data whose second flag is "1". It is only for weighting.

The number of such flag summers 132a to c is determined according to the characteristics of the serial data to be processed. For example, in the case of DVI, 10 bits are processed per reference clock, so that the number of flag adders 132a to c may be 10. .

The partial adders 134a to c include a first half adder 134a for adding the second transition change data and the end result first output from each of the plurality of flag adders 132a to c, and a plurality of flag adders. A middle summer 134b for summing the second transition change data output second from each of the second and second results 132a through c and the third output from each of a plurality of flag summers 132a through c; And a second half adder 134c that adds the two transition change data and the end result.

The lock determination unit 136 determines the lock position for realigning the oversampling data by selecting the largest one among the summation results of each of the partial summers 134a to c. In this case, when the sum of the parts is 4 or more, the transition data is valid. Recognize and perform a lock.

In addition, the lock determining unit 136 performs the locking by designating the start of the data from the first half in the first half, the mid half in the middle half, and the second half in the latter half when the sum of the parts is the largest.

The data estimator 140 rearranges the oversampling data according to the control of the lock controller 130, and the oversampling data approaches a symmetrical form for data recovery.

Here, since the rearranged data may not be symmetrical data due to the transition time and the characteristics of the transmission line, the rearranged data is restored by the data restoration map as shown in Table 4 below.

That is, the data estimator 140 selects the rearranged oversampling data by, for example, a 4-bit window, and estimates the data according to Table 4 below.

Selected Oversampling Data Transition Data Restore data 0000/1111 000 0/1 0001/1110 001 1/0 0010/1101 011 1/0 0011/1100 010 1/0 0100/1011 110 1/0 0101/1010 111 0/1 0110/1001 101 1/0 0111/1000 100 1/0

In Table 4, the selected oversampling data is selected by over 4 bits from the data locked by the lock determination unit 136 of the lock controller 130, the oversampling data input through the transition detector 120, The data corresponding to the selected oversampling data is estimated.
More specifically, as shown in FIG. 4, the oversampling data selected by the 4-bit window restores the double middle bit, that is, the second bit from the lowest to the corresponding data since the lower three bits correspond to the corresponding data. In this case, the first transition is restored in consideration of the position. For example, in the case of "0001", the reconstruction data is "0" which is the second bit from the lowest, but is restored to "1" which is the lower bit because the transition position is the third, that is, the corresponding transition data is "001". In the case of "0100", the reconstruction data is "0". However, since the transition data is "110", the reconstruction data is reconstructed to "1", which is the higher bit. On the other hand, in case of "0101, 1010", since the transition data is "111", it ignores this and restores data by a basic principle. That is, it restores to "0,1".
The data recovery algorithm as shown in Table 4 is generic and may employ other algorithms.

Hereinafter, an operation of a data recovery apparatus for a serial data link according to an embodiment of the present invention will be described with reference to FIG. 4.

4 is a view for explaining an example of data restoration according to an embodiment of the present invention.

First, when the oversampler 110 oversamples the input serial data three times, the primary transition detector 122 divides the transition data between adjacent bits by dividing it into a 4-bit window as shown in FIG. 4. Detect.

The primary transition detection unit 122 generates the first transition change data and the first flag using the primary transition detection map shown in Table 1 using the transition data.

For example, for the first data of oversampling data, that is, "1111", the transition data is "000", and the first transition change data thereof is "000", as shown in Table 1, The 1 flag is "0".

In addition, the transition data is "110" for the tenth data of the oversampled data, that is, "1011", the first transition change data is "010", and the first flag is "1".

Next, the secondary transition detection unit 124 divides the first transition change data into four bit windows, as shown in FIG. 4, and uses the secondary transition detection maps shown in Tables 2 and 3 to change the second transition. Generate data and a second flag.

For example, data input by dividing the lower two bits of the first data and the upper two bits of the second data into one window among the first transition change data, that is, the second transition change data for "0010", are listed in the table. As shown in 2, it is "001" and the second flag follows the current flag value, as shown in Table 3, wherein the current flag value is "0" which is the first value of the first flags.

In addition, the second transition change data for "0110", which is input by dividing the lower two bits of the fourth data and the upper two bits of the fifth data into one window among the first transition change data, is the flag of the previous stage. The flag of the preceding stage corresponds to the fourth data of the first flag, which is "0", so the second transition change data is "001".

Here, as shown in Table 3, the second flag is obtained by performing an AND operation on the preceding flag and the current flag, respectively, and in the above example, the fourth and fifth data of the first flag are each "0". Since each of these operations is logically multiplied by NOT, the result is "1". Therefore, the second flag is "1".

Next, when the flag summer 132 weights the second transition change data by using the second flag, the partial summer 134 divides each of the first half, the middle half, and the second half.

The lock determination unit 136 selects the largest value among the sum values of the respective parts to determine the lock position of the oversampling data.If the sum of each part is the first half, from the first half, and from the middle half, In the latter case, the lock is performed by designating the beginning of the data from the second half.

For example, in FIG. 4, for each of the secondary transition change data, the value of the first half of the first bit is one of the seventh data, so the sum of the first half is 1, and there is no value of "1" in the second bit. The sum is 0, and the value of "1" in the third bit is four from the first to the third and the fifth data, and since the flag of the fourth data is 1, the last half sum is five.

According to this result, when the lock determination unit 136 determines the second half as the lock position, the data estimator 140 designates the second half as a start position among the input oversampling serial data, and divides it into a 4-bit window based on this. The estimated data is estimated using Table 4 below.

For example, in FIG. 4, when the second half of the first oversampling data is based on "1", the first selection data is "1000", and the corresponding reconstruction data is "0" as shown in Table 4 below. to be.

In this way, the incoming serial data can be restored quickly and accurately.

As described above, the data recovery apparatus for the serial data link according to the present invention oversamples the input serial data by three times to detect data transitions between adjacent bits of the oversampling data, and over uses the data transitions. By determining the lock position of the sampling data and estimating the data accordingly, it is possible to recover the data within the reference clock, thus having an effect suitable for a high speed data link.

Claims (5)

A data recovery apparatus for a serial data link having a data estimator having a four-bit window and an oversampler three times the reference clock, Split the oversampled serial data into a 4-bit window and detect data transitions between successive bits to generate first transition change data and a first flag, but if the data transitions are two, the difference between the first transition change data is higher. A plurality of primary transition detectors for inverting the transition bits and setting the corresponding first flag to "1" and other first flags to "0"; Transition data consisting of the lower two bits of the first transition change data of the first stage and the upper two bits of the first transition change data of the rear stage and the second transition change data and the second according to Table 5 below based on each of the first flags. A transition detector composed of a plurality of secondary transition detectors for generating a flag; Receiving the lower 1 bit of the second transition change data of the previous stage and the upper two bits of the second transition change data of the rear stage and the second flag of the preceding stage, and performing an AND operation on the input second transition change data and the second flag, A plurality of flag summers for outputting the AND operation result and the input second transition change data; A partial adder for dividing each output of the plurality of flag adders into a first half, a middle half, and a second half to calculate respective sums; And a lock controller configured to determine a position at which the result of the partial summer is the largest as a lock position of the oversampled serial data. Transition Data Flag of flyer Second transition change data 2nd flag 0010 Don't care 001 Trailing flag 0100 Don't care 010 Trailing flag 1000 Don't care 100 Trailing flag 1001 Don't care 100 Trailing flag 0110 1/0 000/001 ~ (Front flag) and ~ (back flag) 1010 1/0 000/001 ~ (Front flag) and ~ (back flag) 0101 Don't care 000 ~ (Front flag) and ~ (back flag) And others Don't care 000 Trailing flag delete delete The method of claim 1, The partial summer, A first half adder for summing the second transition change data and the end result first output from each of the plurality of flag adders; A mid-sum adder for summing the second transition change data and the end result output second from each of the plurality of flag adders; And a second half adder for summing the second transition change data outputted from each of the plurality of flag adders and the end result. delete

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