KR930015057A - MOS transistor spacer formation method - Google Patents

MOS transistor spacer formation method Download PDF

Info

Publication number
KR930015057A
KR930015057A KR1019910023430A KR910023430A KR930015057A KR 930015057 A KR930015057 A KR 930015057A KR 1019910023430 A KR1019910023430 A KR 1019910023430A KR 910023430 A KR910023430 A KR 910023430A KR 930015057 A KR930015057 A KR 930015057A
Authority
KR
South Korea
Prior art keywords
forming
gate electrode
mos transistor
polycrystalline silicon
silicon substrate
Prior art date
Application number
KR1019910023430A
Other languages
Korean (ko)
Other versions
KR100220299B1 (en
Inventor
위재경
정지현
변상기
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910023430A priority Critical patent/KR100220299B1/en
Publication of KR930015057A publication Critical patent/KR930015057A/en
Application granted granted Critical
Publication of KR100220299B1 publication Critical patent/KR100220299B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 고집적 반도체 소자의 MOS 트랜지스터의 스페이서 형성방법에 관한 것으로, 특히 LDD(Lightly Doped Drain) 구조를 이용한 MOS 트랜지스터 제작시 GGO(Graded Gate Oxide)현상을 방지하며 도핑된 다결정 실리콘으로 된 스페이서를 플로팅 게이트로 사용하여 전류증가 및 노쇠화 현상의 감소를 달성할 수 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a spacer of a MOS transistor of a highly integrated semiconductor device. In particular, when manufacturing a MOS transistor using a lightly doped drain (LDD) structure, it prevents GGO (Graded Gate Oxide) phenomenon and floats a spacer of doped polycrystalline silicon. It relates to a technique that can be used as a gate to achieve an increase in current and a reduction in aging.

Description

MOS 트랜지스터 스페이서 형성방법MOS transistor spacer formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제4도는 본 발명에 의해 MOS 트랜지스터의 스페이서 형성 단계를 도시한 단면도.1 through 4 are cross-sectional views showing a spacer forming step of a MOS transistor according to the present invention.

Claims (3)

MOS 트랜지스터의 스페이서 형성방법에 있어서, 실리콘 기판 상부에 게이트 산화막을 형성하고 그 상부에 게이트 전극을 형성한 다음, 게이트 전극 및 실리콘 기판 상부면에 다결정 실리콘 박막을 형성하는 단계와, 산화 공정으로 상기 다결정 실리콘 박막에 산화막을 형성한 다음, 이온주입공정으로 실리콘 기판에 LDD 영역을 형성하고, 산화막 상부에 질화막 및 산화막을 적층하는 단계와, 게이트 전극을 포함하는 전체구조 상부에 도프된 다결정 실리콘층을 예정된 두께로 형성하고 자기정렬된 건식식각으로 게이트 전극 측벽에 다결정 실리콘 스페이서를 형성하는 단계로 이루어지는 것을 특징으로 하는 MOS 트랜지스터의 스페이서 형성방법.A method of forming a spacer of a MOS transistor, the method comprising: forming a gate oxide film on a silicon substrate, forming a gate electrode on the silicon substrate, and then forming a polycrystalline silicon thin film on the gate electrode and the silicon substrate upper surface; After the oxide film is formed on the silicon thin film, an LDD region is formed on the silicon substrate by an ion implantation process, the nitride film and the oxide film are laminated on the oxide film, and the doped polycrystalline silicon layer is formed on the entire structure including the gate electrode. And forming polycrystalline silicon spacers on the sidewalls of the gate electrodes with a thickness and self-aligned dry etching. 제1항에 있어서, 상기 게이트 전극 및 실리콘 기판 상부면에 형성하는 다결정 실리콘 박막은 20-200Å 정도의 두께로 형성하는 것을 특징으로 하는 MOS 트랜지스터의 스페이서 형성방법.The method of claim 1, wherein the polycrystalline silicon thin film formed on the gate electrode and the upper surface of the silicon substrate is formed to a thickness of about 20-200 μs. 제1항에 있어서, 상기 게이트 전극을 포함하는 전제구조 상부에 형성하는 도프된 다결정 실리콘층은 1500-3000Å 정도의 두께로 형성하는 것을 특징으로 하는 MOS 트랜지스터의 스페이서 형성방법.The method of claim 1, wherein the doped polycrystalline silicon layer formed over the entire structure including the gate electrode is formed to a thickness of about 1500-3000 microns. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023430A 1991-12-19 1991-12-19 Manufacturing method for a spacer of mos transistor KR100220299B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023430A KR100220299B1 (en) 1991-12-19 1991-12-19 Manufacturing method for a spacer of mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910023430A KR100220299B1 (en) 1991-12-19 1991-12-19 Manufacturing method for a spacer of mos transistor

Publications (2)

Publication Number Publication Date
KR930015057A true KR930015057A (en) 1993-07-23
KR100220299B1 KR100220299B1 (en) 1999-09-15

Family

ID=19325187

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910023430A KR100220299B1 (en) 1991-12-19 1991-12-19 Manufacturing method for a spacer of mos transistor

Country Status (1)

Country Link
KR (1) KR100220299B1 (en)

Also Published As

Publication number Publication date
KR100220299B1 (en) 1999-09-15

Similar Documents

Publication Publication Date Title
KR960036040A (en) Ferroelectric memory device and manufacturing method
KR960036041A (en) High breakdown voltage transistor and manufacturing method thereof
KR930006972A (en) Method of manufacturing field effect transistor
KR970003688A (en) Transistor manufacturing method of semiconductor device
JPS55151363A (en) Mos semiconductor device and fabricating method of the same
KR930015057A (en) MOS transistor spacer formation method
KR970004079A (en) Semiconductor device and manufacturing method
KR920005296A (en) Semiconductor Device Separation Manufacturing Method
KR970018685A (en) Semiconductor device with gold structure and manufacturing method thereof
KR970053096A (en) MOS field effect transistor manufacturing method
KR960019768A (en) Transistor Manufacturing Method
KR960019611A (en) Semiconductor device manufacturing method
KR930003430A (en) Semiconductor device and manufacturing method thereof
KR940016927A (en) Method of manufacturing MOS-FET with vertical channel using trench structure
KR970054438A (en) Power MOS device having an inclined gate oxide film and method of manufacturing same
KR960005895A (en) Most transistor manufacturing method
KR0142875B1 (en) Fabrication method of mosfet
KR940012653A (en) Method of manufacturing thin film transistor
KR970054268A (en) Manufacturing Method of Semiconductor SOH Element
KR970024283A (en) MOS transistor and manufacturing method thereof
KR960009216A (en) Semiconductor device and manufacturing method
KR970053895A (en) Structure and Manufacturing Method of CMOS Devices
KR960036021A (en) MOS transistor manufacturing method with low doped drain structure
KR970054104A (en) Manufacturing Method of Semiconductor Memory Device for Improved Refresh
KR910007104A (en) How to Form Self-Aligned Contact

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070518

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee