KR930014796A - Interlayer insulating film formation method for multilayer metal wiring - Google Patents

Interlayer insulating film formation method for multilayer metal wiring Download PDF

Info

Publication number
KR930014796A
KR930014796A KR1019910024091A KR910024091A KR930014796A KR 930014796 A KR930014796 A KR 930014796A KR 1019910024091 A KR1019910024091 A KR 1019910024091A KR 910024091 A KR910024091 A KR 910024091A KR 930014796 A KR930014796 A KR 930014796A
Authority
KR
South Korea
Prior art keywords
metal wiring
insulating film
interlayer insulating
depositing
film
Prior art date
Application number
KR1019910024091A
Other languages
Korean (ko)
Other versions
KR100221607B1 (en
Inventor
전표만
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910024091A priority Critical patent/KR100221607B1/en
Publication of KR930014796A publication Critical patent/KR930014796A/en
Application granted granted Critical
Publication of KR100221607B1 publication Critical patent/KR100221607B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층금속 배선방법에 관한 것으로 특히 절연막의 스텝 커버리지를 개선시키고 보이드(Void) 형성을 방지하는데 적합한 다층금속배선방법에서 다층금속배선시 층간절연막 형성하는 방법에 있어서 1차 금속을 형성하고 PECVD 산화막을 증착시키는 단계(a)와 BSG 막을 증착하는 단계(b)와 PECVD 질화막을 증착시키는 단계(C)를 포함하여 이루어지는 다층금속배선시 층간절연막 형성방법.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layered metal wiring method. In particular, in a multi-layered metal wiring method suitable for improving step coverage of an insulating film and preventing void formation, a primary metal is formed and a PECVD method for forming an interlayer insulating film during multi-layer metal wiring. A method of forming an interlayer insulating film during multilayer metallization, comprising the steps of: (a) depositing an oxide film, (b) depositing a BSG film, and (C) depositing a PECVD nitride film.

Description

다층금속배선시 층간절연막 형성방법.Method of forming interlayer insulating film in multilayer metal wiring.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 층간절연막 도시도.3 is a diagram showing an interlayer insulating film of the present invention.

제4도는 형상비가 높은 경우의 층간절연막 도시도.4 is a diagram showing an interlayer insulating film when the aspect ratio is high.

제3도는 본 발명의 BSG 막 층착장치도 및 증착특성도.3 is a BSG film deposition apparatus and deposition characteristics of the present invention.

Claims (4)

다층금속배선시 층간절연막 형성방법에 있어서, 1차 금속을 위에 PECVD 산화막을 증착시키는 단계(a)와 BSG 막을 증착하는 단계(b)와, PECVD 질화막을 증착시키는 단계(C)를 포함하여 이루어지는 다층금속배선시 층간절연막 형성방법.A method of forming an interlayer dielectric film for multilayer metal wiring, the method comprising: (a) depositing a PECVD oxide film on a primary metal, depositing a BSG film (b), and depositing a PECVD nitride film (C) Method of forming an interlayer insulating film during metal wiring. 제1항에 있어서 단계(a)중 PECVD 산화막의 증착 온도는 250℃이며 증착두께는 0.25㎛인 것을 특징으로 하는 다층금속배선시 층간절연막 형성방법.The method of claim 1, wherein the deposition temperature of the PECVD oxide film is 250 ° C. and the deposition thickness is 0.25 μm during the step (a). 제1항에 있어서 단계(b)중 증착온도는 초기에는 430℃로 하고 말기에는 370℃로 하는 것을 특징으로 하는 다층금속배선시 층간절연막 형성방법.The method of claim 1, wherein the deposition temperature during step (b) is initially set at 430 ° C and at the end of 370 ° C. 제1항에 있어서 단계(b)중 주입붕소(B)의 농도는 초기에 6~7%이고 말기에는 3~4%인 것을 특징으로 하는 다층금속배선시 층간절연막 형성방법.The method of claim 1, wherein the concentration of the boron (B) in the step (b) is 6-7% initially and 3-4% at the end. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910024091A 1991-12-24 1991-12-24 Method of forming inter-metal insulator of multi-layered semiconductor device KR100221607B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024091A KR100221607B1 (en) 1991-12-24 1991-12-24 Method of forming inter-metal insulator of multi-layered semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024091A KR100221607B1 (en) 1991-12-24 1991-12-24 Method of forming inter-metal insulator of multi-layered semiconductor device

Publications (2)

Publication Number Publication Date
KR930014796A true KR930014796A (en) 1993-07-23
KR100221607B1 KR100221607B1 (en) 1999-09-15

Family

ID=19325772

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910024091A KR100221607B1 (en) 1991-12-24 1991-12-24 Method of forming inter-metal insulator of multi-layered semiconductor device

Country Status (1)

Country Link
KR (1) KR100221607B1 (en)

Also Published As

Publication number Publication date
KR100221607B1 (en) 1999-09-15

Similar Documents

Publication Publication Date Title
KR960026671A (en) Manufacturing Method of Semiconductor Device
KR950034482A (en) Method of forming multi-layer metal wiring of semiconductor device
TW356572B (en) Method for forming metal wiring of semiconductor devices
KR930014796A (en) Interlayer insulating film formation method for multilayer metal wiring
KR960035967A (en) Method of forming interlayer insulating film of multilayer metal wiring
KR970003630A (en) Method of manufacturing insulating film between metal wirings of semiconductor device
JPS53107285A (en) Production of wiring structural body
KR980005442A (en) Metal wiring formation method
JPS561547A (en) Semiconductor device
KR930017092A (en) Semiconductor device and manufacturing method
KR960002681A (en) How to Form Multilayer Metal Wiring
KR930014799A (en) Method of growing an insulating film between multilayer metal wiring layers of a semiconductor device
KR950021425A (en) How to Form Multilayer Metal Wiring
KR970018115A (en) Metal wiring formation method of semiconductor device
JPH065605A (en) Electrode wiring method
KR970052389A (en) Contact hole formation method of semiconductor device
KR960005797A (en) Semiconductor Device Wiring Formation Method
KR970077219A (en) Method of forming multilayer wiring of semiconductor device
KR970003652A (en) Manufacturing method of semiconductor device
KR890007397A (en) Method of manufacturing semiconductor device for suppressing hillock formation of metal film
KR970030658A (en) Wiring Formation Method of Semiconductor Device
KR970053588A (en) Method of forming multi-layered metal wiring of semiconductor device
KR920017214A (en) Double interlayer dielectric film deposition method
KR970053555A (en) Method for forming interlayer insulating film of semiconductor device
KR970053587A (en) A semiconductor device manufacturing method comprising a multilayer metal layer

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070518

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee