KR930007108A

KR930007108A - BCH codec with double error correction

Info

Publication number: KR930007108A
Application number: KR1019910015704A
Authority: KR
Inventors: 김영민; 전인산; 박영수
Original assignee: 경상현; 재단법인 한국전자통신연구소
Priority date: 1991-09-09
Filing date: 1991-09-09
Publication date: 1993-04-22
Also published as: KR930011573B1

Abstract

종래의 BCH 코덱은 크게 2가지의 문제점율 안고 있다.The conventional BCH codec has two problem rates.

첫째, 오류위치 다항식의 계수 σ₂를 구하는데 너무 큰 용량의 ROM을 사용하므로 시스템을 구성하는데 매우 어려움이 있으며, 둘째, 특정 길이의 부호어에 대해서만 동작하므로 시스템의 유연성이 떨어지게 되는 것이다.First, it is very difficult to construct a system because the ROM of too large capacity is used to obtain the coefficient σ ₂ of the error position polynomial. Second, the flexibility of the system is reduced because it operates only for a codeword of a specific length.

본 발명은 디지탈 전송시스템에서 데이타를 송수신할때 전송선로상에서 발생하는 오류를 정정하는데 있어서, 오중으로 부터 오류위치 다항식의 계수를 구하기 위해 큰 용량의 ROM을 사용하는 대신 모듈로 2곱셈기와 자승기 등의 연산기를 사용하고, 그리고 오중의 역원을 구하는데만 작은량의 ROM과 랜덤로직을 사용하여 VLSI 칩화가 가능하도록 하고, 또 단축 부호기법을 간단한 논리회로를 구성하여 임의의 길이를 갖는 부호어에 대해서도 2중 오류정정이 가능한 BCH 코덱을 제공함에 목적이 있다.In the present invention, in order to correct an error occurring on a transmission line when transmitting and receiving data in a digital transmission system, a modular multiplier and a multiplier, etc. are used instead of using a large capacity ROM to obtain a coefficient of an error location polynomial from erroneous data. To calculate VLSI chip using small amount of ROM and random logic to calculate the inverse of erroneous number, the short code technique is composed of simple logic circuit to code word of arbitrary length. Another object of the present invention is to provide a BCH codec capable of double error correction.

Description

BCH codec with double error correction

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 BCH 코덱 구성도 및 흐름도,2 is a block diagram and a flowchart of a BCH codec according to the present invention;

제3도는 오류위치 다항식의 계수 생성기의 상세도,3 is a detailed view of the coefficient generator of the error position polynomial,

제4도는 모듈로2(Modulo) 곱셈기의 기본 셀 회로도.4 is a basic cell circuit diagram of a Modulo multiplier.

Claims

An encoder 10 which receives the information word D (x), divides it by the generated polynomial G (x), obtains the remaining r (x), adds it after the information word D (x), and generates a code word C (x), and a transmission line The quintet generator 20 receives r1 (x) or r3 (x) by dividing the received sequence R (x) through the minimum polynomial M1 (x) or M3 (x), and finds S1 or S3 quintet. A buffer 50 receiving the reception sequence R (x), a ROM 30 which receives the errors S1 and S3 and outputs the coefficient σ ₂ of the error position polynomial, and an error position polynomial σ (x) with the error position polynomials σ1 and σ2. BCH composed of an error position detection circuit 40 that calculates an error position by substituting x + a ^j into σ0 + σ1x + σ2x ² and corrects the bit if an error occurs in accordance with the output of the buffer. In the codec design, the buffer 50 has a random length between the buffer generator 20 and the receiver sequence R (x) terminal, not a specific length. A short coder 60 capable of performing a BCH codec function capable of double error correction is also connected to a hore, and between the short coder 60, the fold generator 20 and the error position detection circuit 40 In order to obtain the coefficient σ2 of the error position polynomial, instead of a large capacity ROM, a double error correction is formed by connecting the logic circuit and the ROM 30 so that VLSI chipping is possible using a little ROM and random logic. BCH Cotec available.

2. The coefficient generator of the error position polynomial according to claim 1, wherein the coefficient generator of the error position polynomial is equal to the error S, but the coefficient sigma 2 is S1 ² + S3 / S1. A pentagonal inverse ROM 100 for obtaining the inverse S1 ^-1 of S1 and a modulator two-multiplier 80 for multiplying S3 and S1 ^-1 and an adder 110 to add S1 and S3 S1 ^-1 . BCH codec with double error correction.

3. The BCH codec of claim 2, wherein the modulo double multiplier (80) is composed of a basic cell of AND and XOR.

According to claim 1, wherein the shortened code unit 60 for generating X ⁱ divided into M1 and M3 and input to the quintet generator determines the length i to be shortened, and then operates by an I clock to generate a Xi generator ( 120) and xi / Mi (140) and xi / M3 (150) which divide Xi into the minimum polynomial M1 (x) and M3 (x) and calculate and store the remaining rx1 and rx3 by the Xi generator 120. Multiplication (160), which outputs rx1 * R (x) and rx3 * R (x) multiplied by rx1 and rx3 calculated by the sign (160), and quintet that receives the output of the multiplication and calculates S1 and S3 And a generator (190) and a decoder (130) for adjusting the length of the buffer (180) by receiving the length i to be shortened.

※ Note: The disclosure is based on the initial application.