KR950008489B1 - Decoder for erasor correction under lying 2 symbol - Google Patents

Abstract

The decoding circuit revises the erasure of less than 2 symbols after receiving the Reed-Solomn coded data. It comprises a syndrome accumulator(10), a symbol location indicator(20), an erasure value selector(30), the second erasure section (50), a symbol buffer(BF1) saving symbol data, a flag buffer and accumulator(A5) revising to output.

Description

Decoding Circuit for Erasure Correction of Less Than Two Symbols

1 is a digital communication system diagram

2 is a specific circuit diagram according to the present invention

3 is an operation waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

S0, S1: Syndrome operation register RS0, RS1: Syndrome value storage register

G0, G1: Eraser Position Operation Register

RG0, RG1: Eraser position operation value position operation value register

REG: Symbol position indication register MX1-MX3: Multiplexer

BF1, BF2: Buffer CNT: Counter

LTH: Latch OG1-OG3: Oagate

AG1: Endgate G: Gate

A1-A5: adder M1-M5: multiplier

D1-D2: Calculator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit of Reed-Sololmon Code (hereinafter referred to as "RS" code), and more particularly to a decoding circuit capable of receiving Reed-Solomon coded data and correcting an erasure of 2 symbols or less. It is about.

The R-S code is a non-binary BCH code among Bose-Chaudhuri-Hocquenghem Codes of Cyclic Code and is known as the strongest code for correcting multiple errors.

Referring to FIG. 1, a digital communication process will be described. First, when a code word “c” is transmitted from a transmitter 1, an error “e” flows through the channel 2 and the receiver ( In 3), "r" having an error "e" inserted in the codeword "c" arrives. That is, the transmitting end 1 adds parity " p " for error checking to the pure data " d " to form the codeword " c ", and then transmits it. The error "e" is checked from the relational expression of the pure data "d" and the parity "p", and the error of the corresponding position is corrected when the error "e" is introduced.

Referring to the communication process as described above in detail, in the R-S code code code is represented as follows.

In (1) and (2), c (x) is a code polynomial of a codeword, c is a coefficient of a code polynomial, and Ci is a symbol as a basic data unit.

Therefore, in equation (3), n is the number of symbols and k is the number of data symbols.

The relational expression of the encoding that forms the codeword in Equation (1) in the transmitting end 1 is as follows.

In Equation (4), d (x) is a pure data polynomial, p (x) is a parity polynomial, and the order of the parity polynomial is nkl. C (x) in Eq. (5) is the same value as c (x) in Eq. (4), and G (x) is a Generat Polynomiion al based on α ⁰ -αn- ^ha . x) is quotient.

Therefore, the roots of G (x) are all roots of x (c), as can be seen by the above expression (5), which is a key for error checking and correction.

As described above, the "r" that the codeword formed in the transmitting terminal 1 reaches the receiving terminal 3 through the channel 2 may be expressed by a polynomial as shown in Equation 7 below.

In (7), R (x) is a receiving polynomial and E (x) is an error polynomial that can occur while passing through channel (2).

Note that the addition + operation in the RS code is an XOR (Exclusive OR) operation, the error correction at the receiving end (3), that is, to obtain c (x) from R (x) as shown in Equation (7), E Obtain (x) and XOR to R (x) to perform error correction.

In addition, since an error has occurred for each term of C (X), an error of one symbol of R (x) can be expressed as follows (8) and (9).

Therefore, when an error is introduced as in Equation (9), a syndrome is calculated from a received symbol, an error location polynomial is obtained, an error location is calculated from the error location polynomial, and the error value at the calculated error location is calculated. The error can be corrected by calculating.

Therefore, after finding the position of the error, that is, the symbol of the order term, the error value can be obtained, and the error can be corrected by XORing the term.

The error types are divided into two types. There are two types of error types, as shown in Equation (8) above, an error of not knowing the error value and the occurrence position and an error of knowing the occurrence position. In this case, when the location of the error occurrence such as the former is not known, it is referred to as "error", and the error which knows the location of the error such as the latter is called erasure. The decoding circuit of the receiving end 3 is composed of a primary decoding circuit and a secondary decoding circuit. The primary decoding circuit finds an error occurrence position and corrects an error of the firing number. It is sent to the secondary decoding circuit together. Therefore, the secondary decoding circuit corrects the eraser that cannot be corrected in the primary decoding circuit.

When the secondary decoder circuit is configured under the entirety of correcting only a predetermined number of erasers in the code circuit of the RS code, the configuration and error value for calculating the error position when the correction circuit is implemented by solving the original RS code expression. Since the configuration for calculating the complexity becomes a huge hardware size (hardware size), and the circuit configuration is also complicated, there is a problem that accompanied the difficulty of circuit configuration. Accordingly, an object of the present invention is to provide a circuit capable of correcting two or less erasers in a decoding circuit of an R-S code.

According to another object of the present invention, in a circuit for receiving and decoding a flag and data indicating an error, calculating a polynomial of an error position from the flag, calculating a syndrome of error information from the calculated polynomial, and calculating an error value from the syndrome. In the present invention, a circuit capable of correcting an erasure of two symbols or less by performing an exclusive o- operation on the polynomial and an error value at a position specified by an erasure calculation block is obtained.

Hereinafter, the present invention will be described in detail with reference to the drawings.

를 발생하는 수단만으로 구성되는 연산수단과, 상기 제1신드롬 S₀를 제1 입력신호로 입력하고 상기 제산수단의 출력을 제2입력신호로 수신하는 선택수단을 구비하며, 상기 선택수단이 상기 제1 선택신호 입력시 제1입력신호를 이레이져정정데이타로 선택출력하고 상기 제2 선택신호 입력시 상기 제2 입력신호를 이레이져정정데이타로 선택출력하는 제2 정정부(50)와, 상기 심볼데이타를 저장하는 심볼버퍼(BF1)와, 상기 플래그를 저장하는 플래그버퍼(BF2)와, 상기 제2정정부(50)의 출력을 입력하며, 상기 플래그버퍼(BF2)에서 이레이져플래그 출력시 온되어 상기 이레이저정정데이타의 출력 통로를 형성하는 게이트(G)와, 심볼퍼버(BF1)와 게이트(G)의 출력을 입력하여 정상 심볼일 시 입력되는 상기 심볼데이타를 출력하며 이레이져 심볼일 시 상기 이레이져정정데이타와 입력되는 심볼을 익스클루시브 오아 연산하여 정정 출력하는 가산기(A5)로 구성된다.FIG. 2 is a detailed circuit diagram of a dual erasure correction circuit according to the present invention, and the input and output unit 10 calculates the first syndrome S ₀ and the second syndrome S ₁ by feedback and accumulating depths. Since the symbol position α ⁿ of the highest order term is multiplied by α ⁻¹ for every input clock, the symbol position indicator 20 indicates the position α ¹ of the current input symbol to be input, and the flag is inputted so that the number of erasers is input. An erasure value selection unit 30 for generating a first selection signal at a first erasure symbol position and a second selection signal at a second erasure symbol position, a first erasure operation means and a second erasure operation means; erasure includes a delegation and enter the symbol position information, and a flag, according to the state of the first erasure flag to generate an operation means that the first erasure position information G ₀ by calculating the symbol position information The output "1" during a symbol one and outputting α ⁱ during the first erasure symbol input, and the second erasure symbol input when α ⁱ * α ^j output, and by calculating the symbol position information, the second erasure location The second erasure operation means for generating information G ₁ outputs "0" at the time of the normal symbol according to the state of the flag, outputs "1" at the time of the first erasure symbol, and inputs the second erasure symbol. means for generating S ₀ * α ⁱ by multiplying a first correcting portion 40 for outputting α ⁱ + α ^j , the first syndrome S ₀ and the first erasure position information G ₀ , the multiplication means Means for generating S ₁ + (S ₀ * α ⁱ ) by adding the second syndrome S ₁ and dividing the addition means and second erasure position information G _1;

And means for inputting the first syndrome S ₀ as a first input signal and receiving the output of the division means as a second input signal, wherein the selection means comprises: A second correction unit 50 for selecting and outputting a first input signal as erasure correction data when the selection signal is input, and selecting and outputting the second input signal as erasure correction data when the second selection signal is input; Inputs the symbol buffer BF1 for storing data, the flag buffer BF2 for storing the flag, and the output of the second correcting unit 50, and turns on the erasure flag output from the flag buffer BF2. And input the output of the gate G and the symbol buffer BF1 and the gate G forming the output path of the erasure correction data, and output the symbol data input when the normal symbol is an erasure symbol. The eraser And an adder (A5) for correcting and outputting the correct data by inputting an exclusive ora operation.

2 shows an example of the configuration of a circuit for decoding codewords having 12 data symbols and two parity symbols among 14 symbols in the C (14, 12).

In the above configuration, the syndrome calculation unit 10 applies a symbol generated in the primary decoding circuit to one input terminal of the adders A1 and A2, and the outputs of the adders A1 and A2 are respectively the syndrome calculation registers S0 and S1. ), The first syndrome calculation register 20 calculates the syndrome of the corresponding symbol, outputs the first syndrome, and feeds it back to the other input terminal of the adder A1, and the second syndrome calculation register S1 is applied. Compute the syndrome of the symbol to calculate the second syndrome and apply it to the multiplier (M1), the multiplier (M1) is configured to apply the feedback to the other input terminal of the adder (A2) by multiplying the second syndrome by α. .

The syndrome position indicating unit 20 applies the output of the highest order term position of the received symbol, α12, and the second multiplier M2 to the symbol position indicating register REG, and the symbol position indicating register REG is an inverting agent. The position signal of the corresponding symbol is generated by one clock CK0 and applied to the second multiplier M2, and the second multiplier M2 is configured to multiply the symbol position signal by α- ¹ . Therefore, α ¹ which outputs the symbol position indication register REG becomes position information of the current input symbol.

The erasure value selection unit 3Q inputs the flag to count the number of erasure occurrences of the eraser, the input of the counter CNT, and the counter CNT by the second clock CK1. A means for generating a select signal indicating whether or not there is no erasure or three or more erasures by applying a latch LTH for latching an output and outputs Q2 and Q3 of the latch LTH to the oragate OG1; The output of Q0 and OG1 of latch LTH is applied to OG2 to generate a selection signal indicating whether one eraser is generated, and Q1 and OG1 of latch LTH are generated. Means for generating a signal indicating whether two erasers are generated by applying the output of the "

The first erasure correction unit 40 inputs data " 1 " or first multiplexing data to calculate a first erasure position data G0 and data " 0 " And a second erasure position calculation register G1 for inputting the second multiplexing data to calculate the second erasure position data. The first erasure position calculation register G0 generates the first erasure position data by the first clock CK0 to generate one end and a first eraser of the multiplexer MX1, the multiplier M3, the adder A3, and the like. The multiplier M3 multiplies the output of the symbol position instruction register REG by the first erasure position data and outputs the result to the multiplexer MX1. Inputs a flag output from the first decoding circuit as a selection signal when the outputs of the first erasure position register G0 and the multiplier M3 are input, and according to the state of the flag, the first erasure position calculation register. The first multiplexing data is generated by selecting either G0 or the output of the multiplier M3.The second erasure position calculation register G1 inputs the "0" data and the output of the multiplexer MX2 and then outputs the first multiplexing data. Second erasure position data by clock CK0 And outputs the result of the calculation to the multiplexer MX2, multiplier M4, one end of the adder A3, and the second erasure position value register RG1, wherein the multiplier M4 is provided with the second erasure position data. The output of the symbol position indicating register REG is multiplied and output to the adder A3, which adds the output of the multiplier M4 and the first erasure position data to the other end of the multiplexer MX2. The multiplexer MX2 outputs the second erasure position register G1 and the adder A3, inputs the flag as a selection signal, and generates a second erasure position data or the adder according to the flag signal. The output of A3) is selected to output the second multiplexing data.

The second correction unit 50 applies the first syndrome data and the second syndrome data to the syndrome value storage registers RS0 and RS1 so as to store the first syndrome data and the second syndrome data for the second clock CK1 period, respectively. The output of the syndrome value storage register RS0 is output to the E1 terminal of the multiplexer MX3 and to the multiplier M5. The output of the erasure position value storage register RG1 is output at the time of addition A4. The output of the erasure position operation value storage register RG0 and the output of the syndrome positioning register REG are output to the first divider D1. The output of the first divider D1 is output to the other input terminal of the multiplier M5. The output of the multiplier M5 is output to the adder A4. The output of the adder A4 and the output of the erasure position value storage register RG1 are output to the divider D2. The output of the divider D2 is output to only E2 of the multiplexer MX3. The multiplexer MX3 having the E0 and E3 terminals connected to the ground selects the output of the (E1) terminal by the output of the oragate OG2, and the output of the (E2) terminal by the output of the oragate OG3. Is selected, and otherwise, the outputs of the E0 and E3 terminals are selected and applied to the gate G.

FIG. 3 is an operation waveform diagram of each part of FIG. 2 as c (14,12). It shows that the current input symbol computes the syndrome and eraser position during the codeword period, and performs the eraser correction process for the next coder period, and (4d)-(41) computed the previous state during the 1word period. The process of correcting two erasers with a syndrome value and an eraser position calculation value is shown.

The receiver 3 has primary and secondary decoding circuits as described above. The primary decoding circuit corrects the primary error, and transmits the uncorrected error to the secondary decoding circuit by indicating the position. Data output from the primary decoding circuit is sequentially input from the highest order term in every symbol unit, and a flag is input together with every input symbol as a function indicating whether an error is introduced. The secondary decoding circuit then calculates a polynomial relating to the error location from the flag, and then obtains a syndrome containing information about the error from R (x) as shown in Eq. (9). After that, an error value is obtained from the syndrome and the polynomial of the error position, and the error operation value and R (x) are XORed at the eraser position to perform two or less eraser corrections.

First, the position polynomial should be calculated from the flag indicating the position of the eraser. The eraser position polynomial α (x) can be written as the following equation (10) and (11) when there are two or less erasers.

i) l erasure

ii) two arrayers

In the above formulas, i, j represents the position of the dimension where the erasure occurred.

Secondly, a process of calculating a syndrome containing information on an error is performed. In the encoding process, since all roots of G (x) in Eqs. (5) and (6) are roots of c (x), C (α) °) and C (α °) can be seen that 0.

Therefore, S ₀ = R (α °), S ₁ = R (α '), and S ₀ and S ₁ may be written as in the following Equations (12) and (13).

The error value is then calculated, which can be calculated by the erasure polynomial σ (x) of equations (10) and (11) and syndromes S ₀ and S ₁ of equations (12) and (13).

Here, when the eraser does not flow, the case where one eraser is introduced and two erasers are introduced will be described below.

i) Eraser is not introduced

At this time, S ₀ = 0, S ₁ = 0, and σ (x) = 1, so no correction is necessary.

ii) when one eraser is introduced

Assuming that e (x) = e _i α _i, then S ₀ = e _i , S ₁ = E _i α _j and σ (x) = (x + α ⁱ ), so S ₀ XOR to correct the eraser.

iii) when two erasers are introduced

In this case, since S ₀ = e _i + e _j , S ₁ = e ₁ α _i + e _j α ^j and α (x) = (X + α ^j ) (x + α ^j ), S ₀ , S ₁ And an i-th erasure value and a j-th erasure value at sigma (x), which can be expressed by the following equations (14) and (15).

In formulas (14) and (15), since i, j, α ⁱ , α ^j , S ₀ , S ₁ are already calculated values, _{i i} , e _j can be obtained. Therefore, the eraser is corrected by XORing the error value calculated as described above to the positions of the i-th order and j-th order terms known through the flags.

As described above, a detailed circuit diagram for erasure correction of two symbols may be implemented as shown in FIG. .

The data input terminal 100 sequentially inputs the symbol unit data from the least even term as shown in (4e), and the flag input terminal 101 indicates whether the flag is erased for every symbol (4f). Are simultaneously entered.

Here, the equation (3) is assumed to be c (14,12), which indicates that a total of 14 symbols input are codes having 12 data symbols and 2 parity symbols. At this time, two code word sections such as (4a) from data input to correction are taken as shown in (4b) and (4c) .In the first section, syndrome is calculated through S ₀ and S ₁ from input data. The eraser position is calculated by using G ₀ and G _{1. In the} second section, the output of the S ₀ , S _1, and G ₀ , G ₁ is calculated to perform an eraser correction process.

In the first section of the code word as shown in FIG. 4 (a), the counter CNT also generates a selection signal for selecting the multiplexer MX3 by counting the number of erasers in the input flags, and outputting the counter CNT. The latch LTH latching by the second clock CK1 such as 4i serves to compensate the timing so that the error value can be corrected by calculating an error value in the second section. Therefore, the multiplexer MX3 operates as shown in Table 1 according to the output of the counter CNT.

TABLE 1

In addition, since the symbols and flags must be delayed for one code period, the buffer BF1 outputs the input symbol by delaying one code period (symbol size x 16), and the buffer BF2 delays the flag by one code period. When the symbol to be corrected is output from the buffer BF1, the gate G is turned on to pass the output of the multiplex MX3 as shown in Table 1 to indicate the erasure position. .

The error value output through the gate G is XORed with the output of the buffer BF1 at the adder A5 to correct the erasure. When the erasure is three everyday, the output of the multiplexer MX3 is Since the gate G is " off7 selected " and the " high " signal indicating that the gate G1 cannot be corrected through the AND gate G1 is applied to the signal processor.

Referring to the syndrome calculation process, S0 adds an input symbol as shown by (4e) through the adder A1 and outputs it as follows.

As described above, S ₀ outputs a first syndrome value.

At this time, S1 outputs a symbol input as shown in (4e) through the multiplier M1 and the adder A2 as follows.

Sα as described above outputs a second syndrome value.

At this time, REG is multiplier for every inverted first clock CK0 while α ¹³ is loaded and the S ₀ and S ₁ first and second syndrome values are calculated when the codeword interval starts as shown in (4a) of FIG. α ¹³ -α ^{0, which} is multiplied by α ^{−1 and} corresponding to the symbol time, is output as follows. Thus, REG is α ¹³ , α ¹² , α ¹¹ . , α ⁰ is output.

In order to know whether the symbol is erased at the position indicated by the REG, G ₀ and G ₁ calculate the eraser position value, which is determined by the operation of the multiplexers MX1 to MX2 with or without a flag. That is, the flag indicating that the input of the normal symbol to the multiplexer (MX1) is selecting the output of G _0, so the output of G ₀ is maintained to "1", the erasure being a flag indicating a type of the symbol input when the multiplexer (MX1) is to output a first erasure location data the output of G ₀ indicating the location of occurrence of the symbol erasure so select the output of the multiplier (M3). In addition, if a flag indicating that the input of the normal symbol to the multiplexer (MX2) so selects the output of G _1, the output of G ₁ is kept to "0", the input flag indicating a type of the erasure symbols In this case, since the multiplexer MX2 selects the output of the adder A3 through the multiplier M4, the output of G ₁ generates second erasure position data indicating the erasure generation position of the symbol.

If the above-described operation of S ₀ , S ₁ , REG, G ₀ , G ₁ is performed in the first codeword period, RS ₀ is performed by the second clock CK1 as shown in (4i) of FIG. 4 in the next codeword period. Inputs the output of S ₀ , RS ₁ inputs the output of S ₁ , RG ₀ inputs the output of G ₀ , RG ₁ inputs the output of G ₁ , The erasure is corrected by the clock CK. At this time, the REG indicates the position of the input symbol again, the position of the symbol can be seen that the same position as the output symbol position of RS ₀ , RS ₁ , RG ₀ , RG ₁ .

First, we explain the process when there is no erasure (no erasure). At this time, the output of G ₀ is "1", the output of G ₁ is "0", and the output of OA gate (OG2-OG3) is "0". The multiplexer MX3 outputs "0". At this time, there is no flag output through the buffer BF2. As a result, the gate G performs an "off" operation so that the data through the data buffer BF1 is output as it is without error correction.

Second, the case where one eraser has occurred will be described.

At this time, G0 outputs α ⁱ , G ₁ outputs "1", and since there is one erasure, OA gate (OG2) outputs "1", OA gate (OG3) outputs "0" and the counter because we count one erasure occurs in the (CNT) a multiplexer (MX3) selects the output of the RS ₀ through the E1 terminal. at this time, the erasure symbols wherein RS ₀ is the output e _i flag buffer (BF2) When the gate G is "on" at the position, the e _i is applied to the adder A5. Therefore, the error value e ⁱ is added to the data symbol through the data buffer BF2 (XOR) to correct the eraser. do.

Third, the operation of two erasure generators will be described.

The multiplier M3 outputs α ⁱ × α ^j , and the multiplexer MX1 selects the output of the multiplier M3, so G ₀ outputs α ⁱ × α ^j , and the multiplier M4 outputs α ^j . , Adder A3 outputs α ⁱ -α ^j , multiplexer MX2 selects the output of adder A3, so G1 outputs α ⁱ -α ^j , and counter CNT has two erasers Since multiplexer MX3 selects the output of divider D2 through the (E2) terminal.

Therefore, since RG ₀ outputs α ⁱ × α ^j and REG outputs α ^j , a divider D1 that divides the RG ₀ output by the output of REG outputs α ⁱ .

Therefore, RS ₀ outputs e _i α ⁱ -e _j and RS ₁ outputs e _i + e _j α ^j , so multiplier M5, adder A4 and divider D2 calculate the error value as follows: Done.

Accordingly, it can be seen that the error operation value e _j is applied to the adder A5 when the gate G is "on" by the flag buffer BF2, and XOR is corrected when the corresponding symbol is output from the data buffer BF1.

In FIG. 2, data such as (4k) of FIG. 3 is input to the data input terminal 100, and if a flag such as (41) of FIG. 3 is input to the flag input terminal 101, (4m) of FIG. As shown in (4j) of FIG. 3, the error value is calculated at the corresponding symbol position where the erasure occurs. Where i is the erasure the symbol R ₁₀ by the first erasure occurs where, j is a symbol erasure occurs, the second erasure location is an R _4.

Fourthly, three or more erasures will be described. At this time, the output of the OA gate OG1 is "high", and thus the multiplexer MX3 outputs "0", so that even if the gate G is "on" by the flag buffer BF2, the adder A5 The corresponding symbol is not corrected, and a signal "1" is generated through the AND gate AG1 to inform the signal processor that the error has not been corrected.

As described above, the hardware is constructed using regular form features under the assumption that only up to two erasures are corrected from the RS code, so that the hardware size can be significantly reduced to 1/7 of the circuit solved by the original RS code. In addition, by replacing one block for calculating an error position with one buffer, an arithmetic scheme can be achieved, and the eraser correction function can be easily realized.

Claims (1)

In the erasure correction circuit of Reed-Solomon code which inputs a symbol outputted from the primary decoding circuit and a flag indicating whether or not there is an erasure, the erasure symbol is corrected. A symbol position indicating a position α ¹ of the current input symbol input by multiplying and returning a syndrome operation unit for calculating S ₀ and the second syndrome S ₁ , and multiplying α ⁻¹ at every input clock at α ⁿ , the symbol position of the highest order term An instruction unit, an erasure value selection unit for inputting the flag to count the number of erasures, generating a first selection signal at a first array symbol position, and generating a second selection signal at a second erasure symbol position; And a first erasure operation means and a second erasure operation means, input symbol position information and a flag, and calculate the symbol position information to generate the first erasure position information. Said first erasure means which generates the G _0, the output "1" when in the normal symbol, depending on the state of said flag and outputting α ⁱ during the first erasure symbol input, and the second erasure when the symbol type α ⁱ outputting? ^j , and calculating the symbol position information to generate second erasure position information G ₁ , outputting " 0 " when it is a normal symbol according to the state of the flag. A first corrector for outputting "1" at the first erasure symbol pressure and outputting α ⁱ + α ^j at the time of inputting the second erasure symbol, the first syndrome S ₀ and the first erasure position information G ₀ ; Means for multiplying and generating S ₀ * α ⁱ , means for generating S ₁ (S ₀ * α ⁱ ) by adding the multiplication means and the second syndrome S ₁ , and the adding means and second erasure position information G Divide by ₁

And means for inputting the first syndrome S ₀ as a first input signal and receiving the output of the division means as a second input signal, wherein the selection means comprises: A second correction unit configured to selectively output a first input signal as erasure correction data upon inputting a selection signal and to selectively output the second input signal as erasure correction data when inputting the second selection signal, and to store the symbol data A gate for inputting a symbol buffer, a flag buffer for storing the flag, an output of the second correction unit, and an ON flag output when the erasure flag is output from the flag buffer to form an output passage of the erasure correction data; A symbol buffer and an output of a gate are input to output the symbol data input when the symbol is a normal symbol, and a shim input with the erasure correction data when an erasure symbol. An exclusive Iowa by the adder consisting of correction output decryption operation for erasure correction of the two symbols below, characterized in circuit.

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