KR930006981B1 - Nor ligic mask read only memory device and method for fabricating thereof - Google Patents

Abstract

forming a conduction layer (50) and an insulation film (52) on a substrate (42) to form a film (52) pattern; forming insulation films (56)(58) on the substrate to etch-back the film (56) and layer (50) to form word lines; removing the insulation film (58) to form an insulation film (60); exposing the word line to be programmed, on which the insulation film (52) is formed, to remove the insulation film (52); and exposing the word line to be programmed, on which the insulation film (56) is formed, to remove the insulation film (56). The method forms different insulation films on neighboring word lines respectively, thereby injecting program ions only into the desired cell.

Description

Fabrication method and structure of memory device for reading noah logic mask

1 is a plan view according to a conventional embodiment

2 is a plan view according to another conventional embodiment

3 is an equivalent circuit diagram according to FIG.

4 is a cross-sectional view according to FIG. 2

5 is a plan view according to the present invention

6 is a cross-sectional view according to the present invention

7 is a manufacturing process diagram according to an embodiment of the present invention

8 is a manufacturing process diagram according to another embodiment of the present invention

9 is a manufacturing process diagram according to another embodiment of the present invention

10 is a manufacturing process diagram according to another embodiment of the present invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a mask read only memory (mask ROM) device and a structure thereof, and more particularly to a method of manufacturing a high density NOR logic mask read only memory device and a structure thereof. will be.

In general, a mask reading memory (hereinafter referred to as a mask ROM) is used to store game contents in a control logic such as a microprocessor or a game chip in an information processing system, or widely used in office automation equipment and electronic musical instruments. The recent increase in memory capacity and the high resolution of fonts in office automation equipment, electronic musical instruments, and television game machines. The trend toward higher sound quality demands high-capacity, high-capacity, high-capacity mask roms.

1 is a plan view of a NOR-type mask rom according to a conventional embodiment. A word line 2 extending in a first direction in a horizontal direction and arranged in parallel in a second direction in a vertical direction, an active region 4 extending in the second direction, and overlapping the active region 4 It consists of a bit line 6 and a contact region 8 in which the active region 4 and the bit line 6 are in contact. As can be seen in the figure, since one contact is formed per two bits, there is a problem in that the total area is increased.

2 is a plan view according to another conventional embodiment and is devised by a sharp company, called a flat cell. The quinoa maskrom is disclosed in Symposiun on VLSI Circuit (1988, PP 85-86). A word line 10 extending in the first direction in the lateral direction and arranged in parallel in the second direction in the longitudinal direction and formed of a polycrystalline silicon layer, arranged in parallel in the first direction, and extending in the second direction to n ⁺ Consists of a bit line 12 formed of a diffusion layer. Meanwhile, in the drawing, a channel region formed by passing a word line through two neighboring bit lines is operated as the unit cell 14.

On the other hand, since the bit line is formed of an n ⁺ diffusion layer, the bit line contact is not required for each cell, and it is sufficient to form only one contact per tens of cells in consideration of the resistance of the bit line. In the embodiment shown in the figure, one contact is formed per 32 bits. In addition, since the bit line used as the source or drain of one cell is used as the drain or source of a neighboring cell, the source and drain regions of each cell are reduced by about 1/2.

3 is an equivalent circuit diagram according to FIG. 2. A channel is formed between two neighboring bit lines, and gates in the same row share a word line.

For example, in order to read the selected transistor 14, a power supply voltage (Vcc) of about 5V and a voltage of about 2V are applied to B / L1 and W / L2, and the B / L2 is dished out. And bit lines B / L3,... Of unselected cells. Floats the unselected word lines W / L1, W / L3... Dish. As a result, when the threshold voltage of the selected cell is less than or equal to 2V, the selected cell is turned on so that a current flows, thereby reading the logic " 1 " state. On the other hand, when the threshold voltage of the selected cell is 2V or more, the selected cell is turned off to cut off the current path, thereby reading the logic '0' state. FIGS. 4 (A)-) (B) are shown in FIG. 4 (A) is a cross-sectional view taken along the line a-a ', that is, a cross-sectional view in the word line direction, and FIG. 4 (B) is a cross-sectional view taken along the line b-b', that is, a cross section in the bit line direction. 4A is a diffusion region 12 of the second conductivity type formed in a predetermined region on the first conductivity type semiconductor substrate 16 and used as a bit line, and sequentially on the upper surface of the substrate 16. FIG. And a gate oxide film 20 formed of a silicon oxide film, a word line 10 and an insulating film 22 formed of a polycrystalline silicon layer, and a metal layer 18 over the active region 18. The fourth (B) diagram is shown in FIG. A gate oxide film 20 formed on the upper surface of the first conductive semiconductor substrate 16 and a predetermined region formed on the upper surface of the substrate 16. And the insulating film 22 on the upper surface of the substrate 16. Here, the separation region between the adjacent word lines is limited to a normal photolithography process to form a pattern, whereby the separation interval between the word lines is photographed. In other words, the pattern spacing of the photoresist film is limited by the resolution limit of the mask pattern when forming the pattern by the photo process, so that the minimum separation interval between word lines is less than the limit of the photo process. On the other hand, another obstacle to reducing the spacing between word lines to submicron level is that the process margin is reduced during the ion implantation process for programming the cell.

In other words, when the separation interval is sub-micron level, it is possible to store unwanted data by exposing even neighboring cells to a programmed cell due to misalignment or OVer develop. Therefore, in order to secure the reliability of the product, the word line spacing, which determines the cell spacing, cannot be reduced more than a certain limit, which makes it difficult to implement high integration.

Accordingly, an object of the present invention is to provide a fabrication method and a structure in which the spacing between word lines is submicron in a noah logic mask.

Another object of the present invention is to provide a method for manufacturing a NOR logic mask ROM having a sub-micron word line spacing in a NOR logic mask ROM, and to sufficiently secure a process margin during an ion implantation process for a program. In providing.

In order to achieve the object of the present invention as described above, after forming a pattern of the gate electrode along the odd-numbered or even-numbered word lines, an insulating film having a submicron thickness is formed on the substrate surface, and then a photoresist is applied. Thereafter, an etch back process is performed to form word line intervals corresponding to the thickness of the insulating layer.

In order to achieve another object of the present invention, after forming different insulating films on the upper surface of the adjacent word line, each insulating film is selectively etched by a different etching process.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a plan view of a quinoa mask rom according to the present invention, the word lines 26, 28, 30, 32, and 34 extending in the first direction in the transverse direction and arranged in parallel in the second direction in the longitudinal direction; It consists of bit lines 36, 38, 40 arranged in parallel in one direction and extending in the second direction. In the figure, it can be seen that the spacing between the word lines is formed much narrower than the first and second degrees.

6 (a)-(b) are cross-sectional views of FIG. 5, and FIG. 6 (a) is a cross-sectional view taken along the line C-C ', that is, a cross-sectional view in the word line direction, and FIG. A cross-sectional view taken along the line -d ', that is, a cross-sectional view in the bit line direction. It should be noted that the same numbers are used for the same names as in FIG. 5. 6 (a) shows a second conductive diffusion region 36, 38, 40 formed in a predetermined region on the first conductive semiconductor substrate 42 and a gate oxide film sequentially formed on the upper surface of the substrate 42. 48), a word line 28 formed of a polycrystalline silicon layer, an intermediate insulating film 68, and a metal layer 70 formed on the diffusion regions 36, 38, and 40. 6 (b) shows a plurality of word lines 26, 28, 30, which are arranged at regular intervals on the gate oxide film 48 formed on the upper surface of the first conductive semiconductor substrate 42 and on the upper surface of the gate oxide film 48, respectively. 32 and 34 and an intermediate insulating film 68 on the upper surface of the substrate 42. The second conductive diffusion regions 36, 38, and 40 are used as bit lines.

7 is a manufacturing process diagram of the quinoa mask rom according to the present invention, it should be noted that the same numbers used for the same names as in FIGS. In order to understand the present invention, C-C 'is cut for each process, that is, a cross section of the word line direction and a cross section of the d-d', that is, a cross section of the bit line direction, are shown together. The starting material is a P-type silicon wafer having a resistivity of 18 Ω-cm and a crystal orientation of (100). In FIG. 7 (a) and (a '), an oxidation process is performed in an oxygen (O ₂ ) atmosphere of about 950 ° C. to form a pad oxide film 44 on the upper surface of the semiconductor substrate 42 with a thickness of about 300 kPa. Next, after forming a pattern of the first photoresist 46 by a photolithography process on a predetermined region of the upper surface of the substrate to form a source and drain region to be used as a bit line, Arsenic is added to 6.0E15 ions / cm ^2. Inject the dose with 75KeV of energy. Here, the photoresist pattern is formed according to the bit line in (a), which is a cross-sectional view of the C-C '. The photoresist is formed on the front side. After performing the oxidation step, the n ⁺ ion implantation region may be buried n ⁺ region, and a thick oxide film may be formed on the top of the buried n ⁺ region. In order to adjust the threshold voltage level after removing the first photoresist 46 in FIGS. 7 (b) and (b '), boron was dosed with 1.0E12 ions / cm ² and energy of 30KeV. Inject into. By the above process, the initial state of the cell is enhanced (Enhancenent) type. In FIG. 7C and FIG. 7C, the pad oxide layer 44 is removed by wet etching, and a gate oxide layer 48 having a thickness of about 200 μs is formed on the upper surface of the substrate 42. Next, after forming the first polycrystalline silicon layer 50 having a thickness of about 4000 kHz on the upper surface of the gate oxide film 48, the POCI ₃ is doped so that the resistance is about 20Ω / ㅁ.

Next, a program ion implantation oxide film 52 is formed on the upper surface of the substrate 42 to a thickness of about 7000 Å, and a second photoresist 54 is formed on the upper surface of the substrate 42 to form an odd or even word line. The pattern of the photoresist 54 is formed. Thereafter, the exposed ion implantation oxide film 52 is etched until the surface of the first polycrystalline silicon layer 50 is exposed. After removing the second photoresist 54 in FIGS. 7 (d) and (d '), the nitride film 56 is deposited on the upper surface of the substrate 42 by about 1000 화학 -3000 법 by low pressure chemical vapor deposition. Then, the third photoresist 58 is coated on the upper surface of the substrate 42 to a thickness of about 1 μm, and then etch back until the nitride film 56 on the upper surface of the ion implantation oxide film 52 is sufficiently exposed. Carry out the process. Thus, as shown in FIG. 7 (d '), the third photoresist 58 is left only in a region corresponding to the patterned ion implantation oxide film 52.

The nitride film 56 exposed in FIGS. 7 (e) and (e ') is removed by selective etching. Thereafter, the first polycrystalline silicon layer 50 on the lower surface of the nitride film removed is removed by dry etching. As a result, as shown in FIG. 7E, the surface of the ion implantation oxide film 52 is exposed and the word line 28 is formed in the word line direction. On the other hand, in the bit line direction, as shown in FIG. 7 (e '), a plurality of word lines 26, 28, 30, 32, and 34 are arranged in a line at intervals equal to the thickness of the vaginal film 56 This is done.

In FIG. 7 (f) and (f '), after removing the third photoresist 58 on the upper surface of the nitride film 56, an oxidation process is performed at a temperature of about 900 ° C. to form the word on the upper surface of the substrate 42. An oxide film 60 is formed for insulation between lines. At this time, growth of the oxide film 60 is suppressed by the ion implantation oxide film 52 or the nitride film 56 on the word line, and an oxide film 60 is formed between the word lines.

In order to improve the insulating ability between the word lines, boron (Boron) is placed on the entire surface of the substrate 42 before the oxidation process after removing the third photoresist 58 and a dose of 1.0E13 ionS / cm ² . Ion implantation with energy of 30 KeV may form a channel stop region. Then, after applying the fourth photoresist 62 on the upper surface of the substrate 42, the cell to be programmed in the area protected by the ion implantation oxide film 52 is exposed by a photolithography process to expose the exposed oxide film 52. ). After removing the fourth photoresist 62 from the seventh (g) and (g '), the 55th photoresist 64 is coated on the upper surface of the substrate 42. The exposed nitride film 56 is then removed after exposing the cells to be programmed in the area protected by the nitride film 56 by a photolithography process. The processes shown in Figs. 7 (f) and (f ') and the processes shown in Figs. 7 (g) and (g') may be reversed. In this case, even if an error occurs in the mask alignment and the neighboring cell regions are slightly exposed, the oxide film or the nitride film is formed on the upper portion thereof, and thus is not affected by the etching process.

After removing the fifth photoresist 64 from the seventh (h) and (h ') diagrams, boron is deposited on the entire surface of the substrate 42 with a dose of 1.0-4.0E12 ions / cm ² and an energy of 130-200 KeV. By implanting, cells containing word lines that are not protected by the oxide or nitride film are programmed. In this case, the energy of the ion implanted impurity may pass through the word line and the gate oxide layer under the word line, but may not pass through the word line having the oxide film or the nitride film formed on the upper surface thereof. Thus, by implanting ions into only the desired cell, a programmed cell having a threshold voltage of 2 V or more and an unprogrammed cell having a threshold voltage of 0.6 to 1.0 V are formed. Subsequently, after depositing the intermediate insulating film 68 on the upper surface of the substrate 42, a contact region is formed by a photolithography process, and then a metal layer is formed in a predetermined region to complete the metal electrode 70.

FIGS. 8 (a)-(c ') are manufacturing process diagrams according to another embodiment of the present invention, in particular other embodiments of FIGS. 7 (c) and (c') with respect to FIGS. 7 (e) and (e '). Yes. It should be noted that the same numbers are used for the same names as in FIGS. 5 and 6. It should be noted that the same numbers are used for the same names as in FIGS. 5 and 6. After the process of FIGS. 7 (b) and (b '), the pad oxide layer 44 is wet-etched in FIGS. 8 (a) and (a'), and the gate oxide layer 48 is formed on the upper surface of the substrate 42. ) And the first polycrystalline silicon layer 50 are sequentially formed in a thickness of about 200 mW and about 4000 mW, respectively. Thereafter, the first polycrystalline silicon layer 50 is doped with POCI ₃ so that the resistance thereof is about 20Ω / ㅁ. Next, after forming a program ion implantation oxide film 72 on the upper surface of the substrate 42, the photoresist 74 is coated. A pattern of the photoresist 74 is then formed along the odd or even word lines by a normal photolithography process. Thus, an etching process is performed until the exposed oxide film 72 has a thickness of about 2000 kPa.

After removing the photoresist 74 in FIGS. 8 (b) and (b '), a nitride film 76 having a thickness of 200-500 Å is formed on the upper surface of the substrate 42 by low pressure chemical vapor deposition. Then, the photoresist 78 is applied to the upper surface of the substrate 42 to a thickness of about 1 μm, and then the etch back process is performed until the nitride film 76 on the upper surface of the etched oxide film is sufficiently exposed. Next, the nitride film 76 exposed in FIGS. 8 (c) and (c ') is removed by selective etching. Thereafter, the oxide film 72 for implanting programs and the first polycrystalline silicon layer 50 on the lower surface of the nitride film 76 are removed by dry etching. As a result, the program ion implantation oxide film 72 has a thickness of 5000 kPa and 2000 kPa. As shown in FIG. 8C, the word ion 28 is exposed while the word line 28 is formed. On the other hand, as shown in FIG. 8 (c ') in the bit line direction, a plurality of word lines 26, 20, 30, 32, and 34 are arranged in a line at intervals equal to the thickness of the nitride film 76. Is completed. At the same time, one of the neighboring word lines is protected by an oxide film on its upper surface, and the other is protected by a composite layer in which an oxide film and a nitride film are laminated. Then, the same processes as those described with respect to the seventh (h) and the (h ') in the seventh (f) and (f') are sequentially performed.

In the embodiment of FIG. 7, when the pattern of the program ion implantation oxide pattern is formed, the insulating film for etching the program ion implantation oxide is etched until the surface of the first polycrystalline silicon layer is exposed to form a different insulating film on the upper surface of the adjacent word line. . Thus, word lines of cells to be programmed in different photolithography processes are exposed by using the two types of insulating layers having different etching rates. However, in the embodiment shown in FIG. 8, the etching process is performed such that the program ion implantation sub-layer remains at a predetermined thickness so that an insulating film having the same etching rate is included on the upper surface of the neighboring word line, but using the program difference using the thickness difference. During the injection process, the word lines of the cells that are not programmed are protected. The thickness of the oxide film for program ion implantation remaining here is to be 1/3 or less of the total thickness. Thus, in the etching process of the program ion implantation oxide film to complete the word line and the etching process of exposing a predetermined word line among the word lines protected by the composite layer of the oxide film and the nitride film, as much as the thickness of the program ion implantation oxide film remains. Even if each is etched, a sufficient film thickness is secured to prevent ion implantation during the program ion implantation process.

9 (a)-(c ') are manufacturing process diagrams according to another embodiment of the present invention, in particular, with reference to FIGS. 7 (c) and (c') in FIGS. 7 (e) and (e '). Another embodiment. It should be noted that the same numbers are used for the same names as in FIGS. 5 and 6. In the ninth (a) and (a ') diagrams, the pad oxide layer 44 is wet-etched and then the gate oxide layer 48 and the first polycrystalline silicon having a thickness of about 200 mV and 4000 mV respectively on the upper surface of the substrate 42. After forming the layer 50, POCI ₃ is doped so that the resistance of the first polycrystalline silicon layer 50 is about 20Ω / ㅁ.

Next, the oxide film 80 for program ion implantation is formed on the upper surface of the substrate 42 to a thickness of about 3000 mW, and then a second polycrystalline silicon layer 82 having a thickness of about 4000 mW is formed on the top surface thereof. POCI _{3 is} then doped into the second polycrystalline silicon 82 so that its resistance is about 20Ω / ㅁ. Next, after forming the second photoresist 84 on the upper surface of the substrate 42, a pattern of the second photoresist 84 is formed along the odd-numbered or even-numbered word lines. Then, when the second polycrystalline silicon layer 82 and the program ion implantation oxide film 80 of the exposed region are removed, cross-sectional views in the word line direction and cross-sectional views in the bit line direction are shown in FIGS. 9 (a) and (a '), respectively. same.

After removal of the second photoresist 84 in FIGS. 9 (b) and (b '), a low-temperature chemical vapor deposition method (LPCVD) is performed on the nitride film 86 having a thickness of 2000-3000 mm on the upper surface of the substrate 42. To be deposited.

As a result, the nitride film 86 is formed on the entire surface of the substrate 42 in the cross section b of the word line direction, and the top surface of the second polycrystalline silicon layer 82 is formed on the cross section b ′ of the bit line direction. The nitride film 86 is formed on the side surface, the side surface of the ion implantation oxide film 80, and the exposed upper surface of the first polycrystalline silicon layer 50. Then, the third photoresist 88 is applied to the upper surface of the substrate 42 to a thickness of about 1 μm, and then etch back until the nitride film 86 on the upper surface of the second polycrystalline silicon layer 820 is sufficiently exposed. The third photoresist 88 is left only in a region corresponding to the patterned second polycrystalline silicon layer 82 as shown in FIG. 9 (B ').

The nitride film 86 exposed in FIGS. 9 (c) and (c ') is removed by selective etching. Thereafter, the second polycrystalline silicon layer 82 on the bottom surface of the removed nitride film 86 is removed by dry etching, and then the exposed first polycrystalline silicon layer 50 is etched. As a result, as shown in FIG. 9 (c), the nitride film and the second polycrystalline silicon layer are removed to expose the program ion implantation oxide film 80 and to form a word line 28 in the word line direction. do.

On the other hand, in the bit line direction, as shown in FIG. 9 (c '), a plurality of word lines 26, 28, 30, 32, and 34 are arranged in a line at intervals equal to the thickness of the nitride film 86. Is completed. Then, the same processes as those described with respect to the seventh (h) and the (h ') in the seventh (f) and (f') are sequentially performed.

10 (a)-(d ') are manufacturing process diagrams according to another embodiment of the present invention, in particular, in FIGS. 7 (c) and (c') of FIGS. 7 (f) and (f '). Is another embodiment. It should be noted that the same numbers are used for the same names as in FIGS. 5 and 6.

After the pad coral layer 44 is wet-etched in FIGS. 10A and 10A, the gate oxide layer 48 and the first gate oxide layer 48 having a thickness of about 200 μs and about 4000 μs are formed on the upper surface of the substrate 42, respectively. The polycrystalline silicon layer 50 is formed.

The first polycrystalline silicon layer 50 is then doped with POCI ₃ so that its resistance is about 20Ω / ㅁ. Next, a program ion implantation nitride film 90 and a program ion implantation oxide film 92 are formed on the upper surface of the substrate 42 to have a thickness of about 3000 kPa and about 1000 kPa, respectively, and a second polycrystal having a thickness of about 4000 kPa on the upper surface thereof. The silicon layer 94 is formed. As in the above-described process, POCI ₃ is doped into the second polycrystalline silicon layer 94 so that the resistance is about 20Ω / ㅁ. Next, after forming the second photoresist 96 on the upper surface of the substrate 42, a pattern of the second photoresist 96 is formed along the odd-numbered or even-numbered word lines. Thereafter, the second polycrystalline silicon layer 94, the program ion implantation oxide film 92, and the program ion implantation nitride film 90 in the exposed region are removed. Then, after removing the second photoresist 96 in the 10 (b) and (b '), the nitride film 98 by the low chemical vapor deposition method on the upper surface of the substrate 42 to a thickness of about 200-500Å Form. As a result, the nitride film 98 is formed on the entire surface of the substrate 42 in the cross-sectional view b in the word line direction, and the top surface of the second polycrystalline silicon layer 94 in the cross-sectional view B ′ in the bit line direction. And a nitride film 98 is formed on the side surface, the oxide film 92 for ion implantation, and the upper surface of the exposed first polycrystalline silicon layer 50 and the nitride film 98. Then, the third photoresist 100 is applied on the upper surface of the substrate 42 to a thickness of about 1 μm, and then an etch back process is performed until the nitride film 90 on the upper surface of the second polycrystalline silicon layer 94 is sufficiently exposed. do. Next, the nitride film 98 exposed in FIGS. 10C and 10C 'is removed through selective etching. Thereafter, the first polycrystalline silicon layer 50 on the lower surface of the nitride film 98 is removed by dry etching. As a result, as shown in FIG. 10C, the ion implantation oxide film 92 is exposed and a word line 28 is formed in the word line direction.

On the other hand, in the bit line direction, as shown in FIG. 10 (c '), a plurality of word lines 26, 28, 30, 32, and 34 arranged in a line at intervals equal to the thickness of the nitride film 98 are formed. Is completed.

After removing the third photoresist 100 from FIGS. 10 (d) and (d '), the nitride film 98 exposed on the upper surface of the substrate 42 is removed. In this case, the nitride film 90 for the program ion implantation adjacent to the nitride film 98 is not affected by the etching process by the oxide film 92 formed on the upper surface thereof. Then, the same process as described in the seventh (f) and (f ') is performed. 7 (f) and (f '), an oxide film for insulating the word line is formed between the word lines due to the oxide film and the nitride film formed on the word line upper surface. However, in the embodiment shown in FIG. 10, an oxide film 60a is formed on the exposed upper surface and side surfaces of the word line as shown in FIG. 10 (d '). The thickness of the oxide film formed on the exposed upper surface of the word line is 2000-3000 kPa.

In this case, the growth of the oxide film is suppressed by the nitride film on the word line on which the nitride film is formed.

In the above-described embodiment of the present invention, polycrystalline silicon is used as the conductive layer for forming the word line, but in another embodiment of the present invention, tungsten silicide, titanium salicide, tantalum silicide, or the like may be used.

In addition, within the scope of the technical idea that an insulating film having a different etching rate is formed on a neighboring upper surface of a word line, the oxide or nitride film for implanting programs may be processed or replaced in a reversed process order.

In an embodiment of the present invention, an insulating film for forming word line spacing is formed on the entire surface of the substrate, and then a photoresist is applied to the etch back process. However, in another embodiment of the present invention, instead of the photoresist, a spin on glass (SOG) film, Phospho-Silicate Glass (PSG), and boron silicate glass (Boro-Phospho-Silicatc Glass; BPSG) Etc. can also be used.

Also, in the embodiment of the present invention, the doping concentrations of the first and second polycrystalline silicon layers are the same, but in another embodiment of the present invention, the first polycrystalline silicon layer has a slower etch rate than the second polycrystalline silicon layer. And doping concentration and etch of each of the second polycrystalline silicon layers.

As described above, in the manufacturing method and structure of the quinoa mask rom according to the present invention, an insulating film or a plurality of insulating layers and a second polycrystalline silicon layer are formed on the upper surface of the first polycrystalline silicon layer to form a word line. After the pattern is formed along the even or odd word lines, a nitride film is formed on the substrate surface. After that, a photoresist is applied to the upper surface of the substrate, followed by an etch back process, and then the photoresist is applied, followed by an etch back process, and the exposed nitride film and the first polycrystalline silicon layer or insulating film on the lower surface of the photoresist as a mask. And sequentially etching the first polycrystalline silicon layer to adjust the word line spacing according to the thickness of the nitride film.

Therefore, it is possible to obtain a submicron word line separation interval without being limited by the photolithography process.

In addition, according to the present invention, program ions may be implanted only in a desired cell by forming different insulating layers on adjacent word lines to expose cells to be programmed by different photolithography processes. In other words, even if a misalignment or an excessive phenomenon occurs during photographing, neighboring cells are not affected by the etching process because the neighboring cells are protected by different insulating layers. As a result, sufficient process margin is secured, resulting in increased product yield and increased reliability.

Claims (30)

A word line extended in a first direction in a lateral direction and arranged in parallel in a second direction in a longitudinal direction, and an impurity having a first or second conductivity type arranged in parallel in the first direction and extended in the second direction A method of manufacturing a memory device for readout of a non-logical mask having a bit line formed as a diffusion region, the first conductive layer 50 on an upper surface of a first conductive semiconductor substrate 42 having a gate oxide film 48 formed thereon. The first insulating films 52, 72, 80, 90, 92 and the first insulating films 52, 72, 80 after the first and odd-numbered word lines are formed. A second process of forming patterns of (90, 92) and a third process of forming second insulating films 56, 76, 86, and 98 on the surface of the substrate 42, and the upper surface of the substrate 42 A third insulating film 58, 78, 88, 100 is applied to the second insulating film 56, 76, 76 on the upper surface of the patterned first insulating film 52, 72, 80, 90, 92. ) (86) (9 And etching the exposed second insulating films 56, 76, 86 and 98 until the surface of the substrate 8 is sufficiently exposed, and then etching the exposed second insulating films 56, 76, 86 and 98. The fifth process of forming the word line by etching the first conductive layer 50 on the lower surface of the lower surface of the first insulating layer 58 and the third insulating layer 58, 78, 88, and 100 is removed. (42) A sixth step of forming a fourth insulating film 60 on the upper surface and a word line having the first insulating films 52, 72, 80, 90 and 92 formed on the upper surface of the word line of the cell to be programmed. A seventh process of removing the first insulating films 52, 72, 80, 90, and 92 after exposure by a first photolithography process and a second insulating film 56 on an upper surface of the word line of the cell to be programmed. The eighth process of removing the second insulating films 56, 76, 86 and 98 after the word lines on which the formed lines are formed is exposed by the second photolithography process. Noah logic type, characterized by having a process made A method of manufacturing a memory device for mask reading only. The first insulating layer 52, 72, 80, 90, or 92 of claim 1, wherein an ion of a first or second conductive type impurity is implanted into the entire surface of the substrate 42 after the eighth process. And a step of programming a lower portion of the word line exposed from the second insulating layer (56) (76) (86) (98). The method of claim 2, wherein the ion-implanted impurities are boron, arsenic, phosphorus, and the like. 4. The first conductive layer 50 and the first conductive layer 50 below the first or second insulating layer 50 may pass through the first conductive layer 50 and the gate oxide layer 48 below the first conductive layer 50. And the gate oxide film 48 has an energy that can not pass through. 2. The method of claim 1, wherein the seventh and eighth processes can be performed in a reverse order. The first insulating layer 52, 72 is etched until the surface of the first conductive layer 50 is exposed, or is formed on the upper surface of the first conductive layer 50. A method for manufacturing a memory device for read only memory, characterized in that the etched to have a predetermined thickness thinner than the thickness to be etched. The first insulating layer 56 of claim 6, wherein the second insulating layer 56 formed in the third process is formed when the first insulating layer 52 is etched until the surface of the first conductive layer 50 is exposed. When the first insulating layer 72 is etched to have a predetermined thickness on the upper surface and the side surface of the 52 and the upper surface of the exposed first conductive mold 50, the first insulating film 72 is etched to have a predetermined thickness. And a second insulating film (76) formed in the third step are formed on the top and side surfaces of the first insulating film (72). The method of claim 1, wherein the first insulating films 52, 72, 80 and the second insulating films 56, 76, 86 are etched by different etchant or have different etching rates. A method of manufacturing a memory device for reading a noah logic mask. 9. The noah logic mask dock according to claim 8, wherein the first insulating films 52, 72, and 80 are oxide films or nitride films, and the second insulating films 56, 76, 86 are nitride films or oxide films. Manufacturing method of memory device for power supply. 2. The method of claim 1, wherein the first conductive layer 50 is polycrystalline silicon. 2. The method of claim 1, wherein the first conductive layer 50 is formed of tungsten silicide, titanium silicide, or tantalum silicide. The method of claim 1, wherein the third insulating films 58, 78, 88, and 100 may be formed of a photoresist, a spin on glass film, phosphorus silicate glass, boron phosphorus silicate glass, or an oxide film. A method of manufacturing a memory device for reading a noah logic mask. The method of claim 1, wherein the fourth insulating film (60) is an insulating film between word lines. 15. The method of claim 13, wherein the fourth insulating film (60) is an oxide film. The second conductive layer 82 of claim 1, wherein the second conductive layer 82 is formed on the upper surface of the first insulating layer 80 after the first process. The second conductive layer 82 is formed along an even or odd word line. And forming the pattern of the first insulating film (80) to perform the third step. The method of claim 15, wherein the second conductive layer 82 and the first insulating layer 80 are etched until the surface of the first conductive layer 50 is exposed when the pattern is formed along the even or odd word lines. A method of manufacturing a memory device for exclusive use of a noah logic mask readout, characterized in that. 17. The lone logic mask dock according to claim 16, wherein when the first conductive layer 50 is etched in the fifth process, the second conductive layer 82 on the upper surface of the first insulating layer 80 is simultaneously etched. Manufacturing method of memory device for power supply. 18. The method of claim 17, wherein the first and second conductive layers (50, 82) are polycrystalline silicon. 20. The method of claim 18, wherein the first and second conductive layers 50 and 82 may have different doping concentrations. 20. The doping concentration and etchant of the first and second conductive layers 50 and 82 so that the first conductive layer 50 has a slower etch rate than the second conductive layer 82. Method of manufacturing a memory device for reading a noah logic type mask, characterized in that for adjusting. 16. The method of claim 15, wherein the first insulating layer (80) may be formed of two kinds of films having different etching rates from each other. 22. The cell to be programmed according to claim 21, further comprising removing the third insulating film 88 after the fifth process and then removing the second insulating film 86 remaining on the upper surface of the first conductive layer 50. Removing the first insulating film 80 or the fourth insulating film 60 on the word line of the substrate by a first photolithography process and the fourth insulating film 60 or the first word film of the word line of the cell to be programmed. 1. A method of manufacturing a memory device for exclusive use of a nonalogical mask reading, characterized in that steps of sequentially removing the insulating film (80) by a second photolithography process are performed. 23. The method of claim 22, wherein the first insulating layer (80) has a structure in which a nitride layer and an oxide layer are stacked. 24. The method of claim 23, wherein the second insulating film (86) (98) is a nitride film. The method of claim 1, further comprising ion implanting first conductive impurities into the entire surface of the substrate 42 after the fifth process to form a channel stop region on the substrate between the word lines. A method of manufacturing a memory device for exclusive use of a noah logic mask readout, characterized in that. A word line extended in a first direction in a lateral direction and arranged in parallel in a second direction in a longitudinal direction, and an impurity having a first or second conductivity type arranged in parallel in the first direction and extended in the second direction A mask read-only memory device having a bit line formed as a diffusion region to program a predetermined cell by ion implantation of impurities, the odd word top surface and an odd number of the even word line before performing a photolithography process for program ion implantation. And a first or second insulating layer formed on an upper surface of a first word line, respectively. 27. The memory device of claim 26, wherein the first and second insulating layers have different etching rates or are etched by different etchant. 28. The mask read-only memory device according to claim 27, wherein the first insulating film is an oxide film or a nitride film and the second insulating film is a nitride film or an oxide film. 28. The memory device of claim 27, wherein the first or second insulating film is a composite insulating film in which an oxide film and a nitride film are laminated, and the second or first insulating film is a single insulating film made of an oxide film or a nitride film. 30. The memory of claim 29, wherein when the lower insulating film and the single insulating film of the composite insulating film are formed of the same film quality, the thickness of the single insulating film is more than twice as thick as the thickness of the lower insulating film of the composite insulating film. Device.