KR930004938Y1 - Pulse generator in vtr - Google Patents
Pulse generator in vtr Download PDFInfo
- Publication number
- KR930004938Y1 KR930004938Y1 KR2019880019882U KR880019882U KR930004938Y1 KR 930004938 Y1 KR930004938 Y1 KR 930004938Y1 KR 2019880019882 U KR2019880019882 U KR 2019880019882U KR 880019882 U KR880019882 U KR 880019882U KR 930004938 Y1 KR930004938 Y1 KR 930004938Y1
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- South Korea
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- pulse
- com
- duty
- output
- control pulse
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
- G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
- G11B15/1808—Driving of both record carrier and head
- G11B15/1875—Driving of both record carrier and head adaptations for special effects or editing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
- G11B15/02—Control of operating function, e.g. switching from recording to reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
- G11B27/022—Electronic editing of analogue information signals, e.g. audio or video signals
- G11B27/024—Electronic editing of analogue information signals, e.g. audio or video signals on tapes
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안에 따른 비스/바스 펄스 발생회로도.1 is a bis / bath pulse generating circuit diagram according to the present invention.
제2도는 제1도 각부의 파형도이다.2 is a waveform diagram of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 미분회로 2 : 적분회로1: Differential Circuit 2: Integrating Circuit
3 : 듀티판별회로 4 : 펄스발생부3: Duty discrimination circuit 4: Pulse generator
COM1…COM4: 비교기 Q1…Q3: 스위칭트랜지스터COM 1 ... COM 4 : comparator Q 1 . Q 3 : Switching Transistor
F/F : 플립플롭F / F: Flip-flop
본 고안은 비디오 테이프에 실린 제어펄스를 자동으로 판별하여 테이프의 재편집시 필요한 비스/바스(VISS/VASS)펄스 발생회로에 관한 것이다.The present invention relates to a VIS / VASS pulse generating circuit necessary for automatically recognizing a control pulse loaded on a video tape.
비디오 테이프에 재편집시에는 테이프에 실린 제어펄스에 동기를 맞추어 듀티비(Duty ratio)를 가변시켜 주어야만 하는바 본 고안은 이러한 듀티비를 자동으로 판별하여 듀티비를 자동으로 가변시켜 줌으로써 필요한 시기에 펄스를 선택토록한 비스/바스 펄스 발생회로를 제공하는데 그 목적이 있다.When re-editing on video tape, the duty ratio must be changed in synchronization with the control pulse loaded on the tape. The present invention can automatically determine the duty ratio and automatically change the duty ratio to pulse when necessary. It is an object of the present invention to provide a bis / bath pulse generation circuit for selecting.
이러한 목적을 달성하기 위한 본 고안은 제어펄스를 각각 미분 및 적분하는 회로부와, 적분된 제어펄스의 듀티비를 자동으로 판별하는 듀티판별부 및 듀티판별회로부의 출력을 이용하여 제어펄스의 듀티비를 가변시켜 비스/바스 펄스를 발생시키기 위한 펄스발생부로 구성됨을 특징으로 한다.The present invention for achieving the above object is to use the output unit of the duty cycle of the control pulse and the output unit of the duty discriminating unit and the duty discriminating circuit for automatically determining the duty ratio of the integrated control pulse and the integrated control pulse, respectively. It is characterized by consisting of a pulse generator for generating a bis / bath pulse by varying.
이하, 본 고안을 첨부된 도면에 의거하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 고안에 따른 비스/바스 펄스 발생회로도를 도시한 것이다. 제1도에 도시한 바와 같이 제어펄스를 미분하는 미분회로(1)는 콘덴서(C1)와 저항(R1)으로 구성되고, 적분회로(2)는 저항(R2)과 콘덴서(C2)로 구성된다. 미분회로(1)의 출력단자에는 펄스발생부(4)의 내부에 구성된 스위칭 트랜지스터(Q1)가 연결되고, 트랜지스터(Q1)의 콜렉터에는 콘덴서(C3)와 비교기(COM1)(COM2)가 연결된다. 또한 적분회로(2)의 출력단자에는 듀티판별회로부(3)의 내부에 구성된 비교기(COM3)(COM4)가 연결되며, 비교기(COM3)(COM4)의 출력단자에는 스위칭 트랜지스터(Q2)(Q3)가 각각 연결되는바, 트랜지스터(Q2)(Q3)의 콜렉터는 공접 되어 비교기(COM1)(COM2)에 연결되어 있다.1 shows a bis / bath pulse generation circuit diagram according to the present invention. As shown in FIG. 1, the differential circuit 1 for differentiating the control pulse is composed of a capacitor C 1 and a resistor R 1 , and the integrating circuit 2 is a resistor R 2 and a capacitor C 2. It is composed of The output terminal of the differential circuit 1 is connected to a switching transistor Q 1 configured inside the pulse generator 4, and the collector of the transistor Q 1 is connected to a capacitor C 3 and a comparator COM 1 (COM). 2 ) is connected. In addition, a comparator COM 3 (COM 4 ) configured inside the duty discriminating circuit unit 3 is connected to the output terminal of the integrating circuit 2, and a switching transistor Q is connected to the output terminal of the comparator COM 3 (COM 4 ). 2 ) (Q 3 ) are connected to each other, and the collectors of transistors Q 2 and Q 3 are coupled to each other and are connected to the comparator COM 1 and COM 2 .
그리고 트랜지스터(Q2)(Q3)의 에미터에는 듀티비를 가변시키기 위한 가변저항(VR1)(VR2)이 각각 연결되어 있으며, 비교기(COM1)(COM2)의 출력단자에는 플립플롭(F/F)이 연결되어 있는바, 도면중 미설명부호 R3…R8저항을 표시한다.Variable emitters VR 1 and VR 2 for varying the duty ratio are connected to emitters of transistors Q 2 and Q 3 , respectively. The output terminals of the comparators COM 1 and COM 2 are flipped. The flop (F / F) is connected, unexplained symbol R 3 . R 8 indicates resistance.
이와 같이 구성된 본 고안의 동작을 제1도 및 제2도를 참조하여 설명하면 다음과 같다.The operation of the present invention configured as described above will be described with reference to FIGS. 1 and 2.
제2a도와 같은 제어펄스신호가 미분회로부(1)와 적분회로부(2)에 인가될 경우, 미분회로부(1)는 입력된 펄스를 제2b도와 같이 미분하여 트랜지스터(Q1)의 베이스에 인가하는바, 이때 트랜지스터(Q1)는 턴온되어 순간적으로 콘덴서(C3)에 충전된 전압을 방전시켜 콘덴서(C3)에 재충전이 되도록 한다.When a control pulse signal as shown in FIG. 2a is applied to the differential circuit section 1 and the integrating circuit section 2, the differential circuit section 1 differentiates the input pulse as shown in FIG. 2b and applies it to the base of the transistor Q 1 . bar, wherein the transistor (Q 1) is turned on to discharge the voltage charged to the instantaneous capacitor (C 3) so that the recharging to the capacitor (C 3).
이 경우 콘덴서(C3)의 전압파형은 제2c도에 도시한 바와 같이 된다.In this case, the voltage waveform of the capacitor C 3 is as shown in FIG. 2C.
한편, 콘덴서(C3)가 재충전되는 동안에 적분회로(2)에 인가된 제어펄스는 듀티비에 따라 적분되어 비교기(COM3)의 비반전 단자와 비교기(COM4)의 반전단자에 각각 인가되는바, 이때 비교기(COM3)(COM4)는 트랜지스터(Q2)(Q3)를 스위칭하는 신호를 만들어 낸다.(제2f,g도참조)Meanwhile, the control pulse applied to the integrating circuit 2 while the capacitor C 3 is recharged is integrated according to the duty ratio and applied to the non-inverting terminal of the comparator COM 3 and the inverting terminal of the comparator COM 4 , respectively. In this case, the comparator COM 3 and COM 4 generate a signal for switching the transistor Q 2 and Q 3 (see also 2f and g).
즉, 듀티 27%의 제어펄스의 경우 비교기(COM4)의 출력(제2g도은 하이가 되어 트랜지스터(Q3)의 베이스에 인가되어 트랜지스터(Q3)를 턴온시킨다. 이때 가변저항(VR2)을 조정할경우 플립플롭(F/F)의 출력단(out)에서는 제2동(D)와 같은 신호가 얻어진다.That is, in the case of a duty 27% of the control pulse is applied to the base of the comparator output (claim 2g is a doeun high transistor (Q 3) of the (COM 4) turns on the transistor (Q 3). At this time, the variable resistor (VR 2) In this case, the same signal as the second drive D is obtained at the output end of the flip-flop F / F.
또한, 듀티 60%의 제어펄스일경우, 비교기(COM3)의 출력(제2f도)은 하이가 되어 트랜지스터(Q2)가 턴온하게 되는바, 이때 가변저항(VR1)을 조정하면 플립플롭(F/F)의 출력단(out)에서는 제2e도와 같은 신호가 얻어진다. 따라서, 비교기(COM4)의 출력이 하이 상태일 경우에 플립플롭(F/F)의 출력은 제2d도만이 선택되고, 비교기(COM3)의 출력이 하이일경우에는 플립플롭(F/F)의 출력은 제2e도만이 선택된다. 따라서, 플립플롭(F/F)의 최종출력은 제2h도와 같이 얻어진다.In the case of a control pulse of 60% duty, the output of the comparator COM 3 (FIG. 2f) becomes high and the transistor Q 2 is turned on. When the variable resistor VR 1 is adjusted, the flip-flop is adjusted. At the output (out) of (F / F), a signal similar to that in Fig. 2e is obtained. Accordingly, when the output of the comparator COM 4 is high, the output of the flip-flop F / F is selected only in the second d degree, and when the output of the comparator COM 3 is high, the flip-flop F / F is high. Output is selected only for the second e. Therefore, the final output of the flip flop F / F is obtained as shown in FIG. 2h.
이와 같이 동작하는 본 고안은 듀티비를 자동으로 판별하여 원래의 펄스에 동기를 맞추어 듀티를 자동으로 가변시켜 줌으로써 필요한 시기에 펄스를 용이하게 선택함으로써 비디오 테이프를 재편집할 수 있는 특징을 지닌 것이다.The present invention, which operates as described above, has the characteristic of automatically re-editing the video tape by automatically selecting the duty ratio when necessary by automatically determining the duty ratio and automatically changing the duty in synchronization with the original pulse.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880019882U KR930004938Y1 (en) | 1988-12-02 | 1988-12-02 | Pulse generator in vtr |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880019882U KR930004938Y1 (en) | 1988-12-02 | 1988-12-02 | Pulse generator in vtr |
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| Publication Number | Publication Date |
|---|---|
| KR900013209U KR900013209U (en) | 1990-07-05 |
| KR930004938Y1 true KR930004938Y1 (en) | 1993-07-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880019882U KR930004938Y1 (en) | 1988-12-02 | 1988-12-02 | Pulse generator in vtr |
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| KR (1) | KR930004938Y1 (en) |
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1988
- 1988-12-02 KR KR2019880019882U patent/KR930004938Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR900013209U (en) | 1990-07-05 |
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