KR930004641Y1 - Dual inverter gate array cell - Google Patents

Abstract

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Description

Dual Inverter Gate Array Cells

Figure 1a is a conventional single inverter gate array cell structure diagram, (b) is an equivalent circuit diagram of a single inverter gate array cell.

FIG. 2A is a schematic diagram of a typical NOR gate array cell, and (b) is an equivalent circuit diagram of a NOA gate according to FIG. 2A.

Figure 3a is a dual inverter gate array cell structure diagram according to the present invention, (b) is an equivalent circuit diagram of a dual inverter according to Figure 3a.

4 is a circuit diagram of an embodiment using a dual inverter gate array cell according to the present invention.

* Explanation of symbols for main parts of the drawings

1 to 4: Polygate P1, P2: PMOS transistor

N1, N2: NMOS transistor A: Primary metal layer

a: Primary metal contact B: Secondary metal layer

b: Viacontech

The present invention relates to a base array for a gate array in an application specific IC (ASIC) design, in particular, to improve the inefficiency due to the unused gate when only a single inverter is formed in the base array for the gate array. An inverter gate array cell.

In general, in the circuit design using the gate array, the unit of the smallest cell is composed of four polygates, and the two gates on the side for applying the positive power supply (V _DD ) are applied to the PMOS gate, and the ohmic power supply (Vss) is applied. The two gates of the side to be used as the NMOS gate.

The NAND, NOA, or inverter gate may be configured by changing the layout of the contact and the metal layer in the basic cell.

FIG. 1A is a structure diagram of a conventional single inverter gate array cell. As shown in FIG. 1A, PMOS transistors P1, P2 and NMOS transistors N1 and N2 are formed as primary metal layers by primary metal contacts, respectively. Positive power supply lines (V _DD ) and ohmic power supply (Vss) lines are formed, and the polygate 1 of the PMOS transistor P1 and the polygate 2 of the NMOS transistor N1 are formed by primary metal contact. In addition to connecting with a metal layer, a via contact is formed on the primary metal layer to use an input (IN) terminal, and the source of the PMOS transistor P1 and the drain of the NMOS transistor N1 are 1. The primary metal layer was connected to the primary metal layer by the primary metal contact, and the primary metal layer was used as the OUT terminal.

FIG. 1B is an equivalent circuit diagram of the single inverter cell according to FIG. 1A. As shown in FIG. 1B, the gates of the PMOS transistor P1 and the NMOS transistor N1 are commonly connected and used as an input IN terminal. The drain of the PMOS transistor P1 and the source of the NMOS transistor N1 are connected in common and used as an output OUT terminal, and a positive power supply V _{DD is} connected to the source of the PMOS transistor P1 to the NMOS transistor. The ohmic power supply Vss is connected to the source of N1.

FIG. 2A is a schematic diagram of a typical NOR gate array cell, and FIG. 2B is a NOR gate equivalent circuit diagram according to FIG. 2A. As shown in FIG. 2A, the PMOS transistor P1 includes four polygates 1 to 4. In the basic gate array cell forming (P2) and the NMOS transistors (N1) and (N2), the positive power source (V _DD ) line is connected to the source of the PMOS transistor P1 by a primary metal layer by primary metal contact. The ohmic power supply (Vss) line is connected to the source of the NMOS transistors N1 and N2 by a primary metal layer by primary metal contact, and the poly gate 1 and the N of the PMOS transistor P1 are connected. The poly gate 3 of the MOS transistor N1 is connected to the primary metal layer by the primary metal contact, and via contacts are formed on the primary metal layer to form the first input IN1 terminal. The polygate 2 of (P2) and the polygate 4 of the NMOS transistor N2 are primary Via contact is formed in the primary metal layer by de-contact, and a via contact is formed in the primary metal layer to form a second input IN2 terminal. The drain of the PMOS transistor P2 and the NMOS transistor N1 are formed. The drain of (N2) is connected to the primary metal layer by the primary metal contact so that the primary metal layer becomes an output (OUT) terminal.

That is, as shown in the equivalent circuit of FIG. 2b, inputs IN1 and IN2 are applied to the gates of the PMOS, NMOS transistors P1, N1, and P2, N2, respectively, and the PMOS transistor P2. ) And the output (OUT) through the common drain point of the drain of the NMOS transistor (N1, N2).

When comparing the inverter gate and the noah gate using a conventional gate array basic cell configured as described above are as follows.

In general, a basic cell composed of four polygates is used. The inverter gate uses only two polygates P1 and N1, and does not use the remaining two polygates P2 and N2.

This is because the basic inverter gate can be realized by using only one PMOS transistor and one ENMOS transistor.

However, the reason why the basic cell is composed of four polygates is to realize the desired gate by using all four polygates in the noble gate or the NAND gate, as shown in the noble gate.

Therefore, when configuring the gate array, there is no problem in configuring the noah gate or the NAND gate. However, in the case of configuring only the single inverter as the basic cell, one basic cell is required per inverter gate. As a result, polygates that are not used are created, which makes them inefficient.

In view of such a problem, the present invention realizes two inverter gates in one basic cell when configuring an inverter in a gate array basic cell so that two or more inverters can be used in designing a circuit requiring two inverters. The dual inverter gate array cell was designed to increase the utilization efficiency and reduce the total chip area, which will be described in detail with reference to the accompanying drawings.

FIG. 3a is a schematic diagram of a dual inverter gate array cell according to the present invention, and FIG. 3b is an equivalent circuit diagram of FIG. 3a. FIG. 3a shows a PMOS transistor in which polygates 1, 2, 3, and 4 are formed, respectively. (P1), (P2) and NMOS transistors (N1), (N2), the positive power line is formed on the PMOS transistors (P1), (P2) side by the primary metal layer by the primary metal contact, In a gate array basic cell in which a negative power supply (Vss) line is formed of a primary metal layer by primary metal contact on the NMOS transistors N1 and N2, the PMOS transistors P1 and P2 After connecting the polygates (1) and (2) and the polygates (3) and (4) of the NMOS transistors (N1) and (N2) to the primary metal layer by primary metal contact, respectively, each primary metal The via metal is formed on the layer to be the input (IN1) and (IN2) terminals, respectively, and the primary metal layer is formed by the primary metal contact which connects the source of the PMOS transistor P1. The primary metal layer by the primary metal contact connecting the drain of the NMOS transistor N2 is connected to the secondary metal layer through the via contactor as a secondary metal layer so as to be separated from the input (IN1) metal layer. An output OUT1 terminal of the first inverter, and the primary metal layer connecting the source of the PMOS transistor P2 by the primary metal contact and the drain of the NMOS transistor N2 to the primary metal contact. The primary metal layer connected by the second metal layer was connected to the secondary metal layer via the viacontec to be separated from the input (IN2) metal layer, and the secondary metal layer was configured to be the output (OUT2) terminal of the second inverter.

That is, as shown in FIG. 3B, the inverters are configured using PMOS, NMOS transistors P1, N1, and P2, N2 each having polygates (1, 3) (2, 4). Inverters were realized.

In the dual inverter gate array cell according to the present invention configured as described above, the PMOS polygate 1 and the NMOS polygate 3 are connected to the primary metal layer by the primary metal contactor, and the primary metal layer is connected to the viacontech. The first metal layer connected to the input IN1 terminal of the first inverter and connected to the drain of the PMOS transistor P1 and the drain of the NMOS transistor M by the primary metal contact to Viacontec. By connecting to the secondary metal layer by connecting the secondary metal layer to the output (OUT1) terminal, to configure a first inverter using two polygates (1), (3), the same as the first inverter The second inverter was constructed using two polygates 2 and 4 in the layout.

Therefore, in the application example circuit using the dual inverter gate cell according to the present invention as shown in FIG. 4, a noah gate NOR1 consisting of one basic gate array cell and one dual inverter gate cell according to the present invention The first inverter I1 and the second inverter I2 and the NAND gate NAND1 constituted by one basic gate array cell are configured.

That is, in the circuit of FIG. 4, two inverters I1 and I2 are required. When the conventional single inverter gate array cell is used, one basic gate array cell for the first inverter I1 and the second inverter ( One base gate array cell is required for I2) and two base gate array cells are required for two inverters I1 and I2. However, if a dual inverter gate array cell according to the present invention is used, one basic gate array cell is required. Since two inverter gates are implemented in the array cell, two inverters I1 and I2 required in FIG. 4 can be realized as the dual inverter gate array cell according to the present invention, which is one basic gate array cell.

As described above, in the present invention, in the base gate array cell having four polygates, in the prior art, only one inverter is configured with one basic gate array cell when the inverter is implemented. By implementing in an array cell, the placement of the Auto Place and routing cells is much closer, reducing the length of the wires, thus resulting in a reduction in chip size and wire length. The delay time can be reduced, and the chip size is reduced, thereby reducing the production cost.

Claims (1)

In the basic gate array cell including the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 in which the poly gates 1 to 4 are respectively formed, the PMOS transistors P1 and ( The primary metal layer is connected to the source side of P2) with a primary metal contact to form a positive power supply (V _DD ) line, and the primary metal contact is primary to the source side of the NMOS transistors (N1) and (N2). A metal layer is connected to form an ohmic power (Vss) line, and the PMOS polygates (1), (2), and the NMOS polygates (3) and (4) are primary metal layers, respectively. The primary metal layer is connected to each of the input (IN1) and (IN2) terminals via viacontec and connected to the drain of the PMOS transistors (P1) and (P2) and the primary metal contact, respectively. The primary metal layer connected to the drains of the NMOS transistors (N1) and (N2) and the primary metal layers, respectively, to the secondary metal layers via viacontec. Dual inverter gate eoraeyi cell to form a connection to each of the secondary output of each metal layer (OUT1), (OUT2), characterized in that the terminals of two inverter gate structure.