KR20000026268A - D flip-flop circuit - Google Patents

Abstract

PURPOSE: A D flip-flop having a miniaturized composition is provided to reduce the size of cells and the size of chips. CONSTITUTION: A D flip-flop circuit comprises a first inverter, a second inverter, a reverse circuit, a third inverter, a first transmission gate, a first logic circuit, a second logic circuit, a second transmission gate, a fourth inverter, a fifth inverter, and a sixth inverter. The first inverter reverses a clock signal. The second inverter reverses the reversed clock signal. The reverse circuit is controlled by the clock signal reversed via the first and the second inverter, and reverses an input signal. The third inverter reverses the reversed input signal. The first transmission gate is controlled by the clock signal reversed through the first/the second inverter, and transfers the input signal reversed via the third inverter. The first logic circuit is controlled by the clock signal reversed via the first and second inverter, and operates the input signal and a reset signal in NAND. The second logic circuit operates the input signal in NAND transferred through the reset signal and the first transmission gate inverter. The second transmission gate is controlled by the reversed clock signal through the first and the second inverter, and transfers the input signal transferred through the first transmission gate. The fourth inverter reverses an output of the second logic circuit. The fifth inverter reverses an output of the second transmission gate. The sixth inverter has an input terminal connected to current paths, which are formed between the input of the fourth inverter and the output of the second logic circuit, and an output terminal connected to current paths, which are formed between the output terminal of the second transmission gate and the input of the fifth inverter.

Description

D FLIP-FLOP CIRCUIT

TECHNICAL FIELD The present invention relates to logic circuits, and more particularly to a de-flip-flop circuit of a new structure.

1 is a circuit diagram showing a de-flip-flop circuit according to the prior art.

Referring to FIG. 1, a conventional D flip-flop circuit includes seven inverters 10, 12, 14, 20, 30, 32, 34 and four transfer gates 16, 18, 22. , 26), and two NAND gates 24 and 28.

An input terminal of the inverter 10 is connected with a clock signal CK and an output terminal is connected with an input terminal of the inverter 14. The input terminal of the inverter 12 is connected with the input signal D and the output terminal is connected with the input terminal of the transmission gate 16. The transfer gate 16 is composed of one PMOS transistor 40 and one NMOS transistor 42, the gate of the transistor 40 being connected to the output terminal of the inverter 14, the transistor 42 The gate of is connected to the output terminal of the inverter 10. In addition, the transfer gate 18 is composed of one PMOS transistor 44 and one NMOS transistor 46, the gate of the transistor 44 is connected to the output terminal of the inverter 10, the transistor ( The gate of 46 is connected to the output terminal of the inverter 14.

An input terminal of the inverter 20 is connected to an output terminal of the transmission gate 16. The transfer gate 22 is composed of one PMOS transistor 50 and one NMOS transistor 48, the gate of the transistor 48 being connected to the output terminal of the inverter 14, the transistor 50 The gate of is connected to the output terminal of the inverter 10.

The NAND gate 24 is composed of two PMOS transistors 52 and 54 and two NMOS transistors 56 and 58. Current paths of the PMOS transistor 54 and the NMOS transistors 56 and 58 are sequentially formed in series between a power supply voltage and a ground voltage, and gates of the PMOS transistor 54 and the NMOS transistor 58 are connected to the inverter. The signal output from 20 is controlled. The gate of the NMOS transistor 56 is controlled by a reset signal / RESET. The current path of the transistor 52 is connected to the power supply voltage and one end of the current paths of the transistors 54 and 56 and is also connected to the transfer gate 18, the gate of which is Controlled by a reset signal (/ RESET).

The transfer gate 26 is composed of one PMOS transistor 62 and one NMOS transistor 60, the gate of which is connected to the output terminal of the inverter 10, and the transistor 62. ) Is connected to the output terminal of the inverter (14).

One input terminal of the NAND gate 28 is connected to the reset signal / RESET, and the other input terminal is connected to an output terminal of the transmission gate 22. The input terminal of the inverter 32 is connected to the output terminal of the NAND gate 28, and the output terminal is connected to the first output terminal Q of the de-flip-flop circuit. The input terminal of the inverter 34 is connected to the output terminal of the transmission gate 26, and the output terminal is connected to the second output terminal / Q. An input terminal of the inverter 30 is connected to an output terminal of the NAND gate 28, and an output terminal is connected to one end of current passages of the transmission gate 26 and the inverter 34.

As shown in the figure, the de-flip-flop with a reset terminal in the STD80 library (channel length: 0.5 μm) is a logic circuit 70 with one inverter and one transfer gate, one transfer gate and one NAND Logic circuit 80 having a gate.

As is well known, an inverter consists of one PMOS transistor and one NMOS transistor, and the transfer gate also consists of one PMOS transistor and one NMOS transistor. The NAND gate also consists of two PMOS transistors and two NMOS transistors. Thus, the de-flip-flop circuit consists of 15 PMOS transistors and 15 NMOS transistors, all of which include 30 transistors.

Integrating the largest cells in the smallest area has a significant impact on production cost savings. In other words, if a cell having the same function is reduced in size, a logic circuit that performs more functions with the same number of gates may be implemented. In particular, when using a QLM (quaternary metal) or higher process, since the chip utilization is 90% or more, a decrease in cell size means a decrease in chip size.

Accordingly, it is an object of the present invention to provide a de-flop of a new miniaturized structure.

1 is a circuit diagram showing a de-flip-flop circuit according to the prior art;

2 is a circuit diagram showing a configuration of a de-flip-flop circuit according to a preferred embodiment of the present invention;

Figure 3a is a view showing a layout structure of a conventional de-flip-flop circuit, Figure 3b is a view showing the layout structure of a de-flip-flop circuit according to the present invention.

* Description of the symbols for the main parts of the drawings *

10, 12, 14, 20, 28, 32, 34, 100, 102, 116, 118, 120: lsqjxj

16, 18, 22, 26, 24, 110, 114: transmission gate

28, 24, 112: NAND Gate

According to a feature of the present invention for achieving the object of the present invention as described above, the de-flip-flop circuit includes a first inverter for inverting the clock signal; A second inverter for inverting the inverted clock signal; An inversion circuit controlled by the inverted clock signals through the first and second inverters to invert the input signal; A third inverter for inverting the inverted input signal; A first transmission gate controlled by the clock signals inverted through the first and second inverters to transfer the input signal inverted through the third inverter; A first logic circuit controlled by the inverted clock signals through the first and second inverters to NAND-operate the inverted input signal and the reset signal through the third inverter; A second logic circuit for NAND-operating the reset signal and the input signal transferred through the first transfer gate; A second transmission gate controlled by clock signals inverted through the first and second inverters to transfer the input signal transmitted through the first transmission gate; A fourth inverter for inverting the output of the second logic circuit; A fifth inverter for inverting the output of the second transfer gate; An output terminal connected to current paths formed between an output terminal of the second logic circuit and an input of the fourth inverter, and an output terminal connected to current paths formed between an output terminal of the second transmission gate and an input of the fifth inverter. And a sixth inverter having.

In a preferred embodiment, the inversion circuit comprises: a first PMOS transistor having one current path and controlled to the input signal; A second PMOS transistor having one current path and controlled to the clock signal inverted through the second inverter; A first NMOS transistor having one current path and controlled to the clock signal inverted through the first inverter; A second NMOS transistor having one current path and controlled to the input signal, wherein the current paths of the transistors are sequentially formed in series between a power supply voltage and a ground voltage.

In a preferred embodiment, the first logic means comprises: a first PMOS transistor having a first current electrode, a second current electrode, and a gate controlled to the reset signal; A first current electrode connected to the first current electrode of the first transistor, a second current electrode connected to the second current electrode of the first transistor, and a gate controlled to the clock signal inverted through the third inverter. 2 PMOS transistors; A third PMOS transistor having one current path and controlled to the clock signal inverted through the first inverter; A first NMOS transistor having one current path and controlled to the clock signal inverted through the second inverter; A second NMOS transistor having one current path and controlled to the input signal inverted through the third inverter; And a third NMOS transistor having a current path and controlled to the reset signal, wherein the third PMOS transistor and the first to third NMOS transistors are connected to a second current electrode of the first and second PMOS transistors. It is sequentially formed in series between the ground voltages.

(Action)

By such a device, a miniaturized new de-flip-flop circuit can be realized.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, specific details are set forth in detail, for example, in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

2 is a circuit diagram showing the configuration of a de-flip-flop circuit according to a preferred embodiment of the present invention.

Referring to FIG. 2, the de-flip-flop includes six inverters 100, 102, 106, 116, 118, and 120, an inverting circuit 104, a logic circuit 108, and a NAND gate 112.

The inverter 100 inverts the clock signal CK, and the inverter 102 inverts the inverted clock signal / CK.

The inverting circuit 104 includes two PMOS transistors 130 and 132 and two NMOS transistors 134 and 136, so that the clock signals CK, which are inverted through the inverters 100 and 102, / CK) to invert the input signal D. Current paths of the transistors 130, 132, 134, 136 are sequentially formed in series between the supply voltage and ground. The transistors 130 and 136 are controlled to the input signal D, respectively. The transistor 132 is controlled by the clock signal CK inverted through the inverter 102, and the transistor 134 is controlled by the clock signal / CK inverted through the inverter 100. .

The inverter 106 inverts the inverted input signal / D output from the inversion circuit 104.

The transfer gate 110 includes one PMOS transistor 150 and one NMOS transistor 152, and is controlled by clock signals inverted through the inverters 100 and 102 to control the inverter 106. Transfer the input signal (D) inverted through.

The logic circuit 108 includes three PMOS transistors 138, 140, 142 and three NMOS transistors 144, 146, 148, inverted through the inverters 100 and 102. The NAND operation is performed on the input signal D and the reset signal / RESET which are controlled by the signals / CK and CK and are inverted through the inverter 106. The transistors 138 and 148 are controlled by the reset signal / RESET, and the transistors 140 and 146 are controlled by the inverted input signal D through the inverter 106. The transistor 142 is controlled to the inverted clock signal / CK through the inverter 100 and the transistor 144 is controlled to the inverted clock signal CK through the inverter 102.

The NAND gate 112 performs a NAND operation on the reset signal / RESET and the input signal D that is sheared through the transmission gate 110. The inverter 118 inverts the output signal of the NAND gate 112. The output signal of the inverter 118 becomes the first output signal Q of the de-flip-flop circuit.

The transmission gate 114 is controlled by the clock signal / CK inverted through the inverter 100 and the clock signal CK inverted through the inverter 102 to transfer the output of the transmission gate 110. do. The inverter 120 inverts the output signal of the transfer gate 114. The output signal of the inverter 120 becomes the second output signal / Q of the de-flip-flop circuit.

The inverter 116 may include an input terminal connected to current paths between an output terminal of the NAND gate and an input terminal of the inverter 118, and current paths between an output terminal of the transfer gate 114 and an input terminal of the inverter 120. It has a connected output stage.

Figure 3a is a view showing a layout structure of a conventional de-flip-flop circuit, Figure 3b is a view showing the layout structure of a de-flip-flop circuit according to the present invention.

In the logic circuit 80 of the conventional de-flip-flop circuit shown in FIG. 1, a node N1, which is a current path between the transfer gate 18 and the NAND gate 16, is contacted as shown in FIG. 3A. The contacts are contacts 202 for connecting transistors 44 and 54 and contacts 204 for connecting transistors 46 and 56, respectively. A contact is also formed between the inverter 12 and the transfer gate 16 of 70. The contacts 202, 204 are located between the gates 206, 208, and 210, thereby increasing the cell size. It becomes a factor.

In the present invention, by replacing the conventional logic circuit 70 with the inversion circuit 104, and by replacing the logic circuit 80 with the logic circuit 108, as shown in Figure 3b, the nodes (N2) and (N3) Contacts are not formed. Therefore, the width D2 of the nodes N2 and N3 is smaller than the width of the conventional node N1. As the width D2 decreases, the drain capacitance decreases, thereby reducing the cell delay.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, it is possible to implement a de-flip-flop circuit of a new miniaturized structure.

Claims (3)

A first inverter for inverting the clock signal; A second inverter for inverting the inverted clock signal; An inversion circuit controlled by the inverted clock signals through the first and second inverters to invert the input signal; A third inverter for inverting the inverted input signal; A first transmission gate controlled by the clock signals inverted through the first and second inverters to transfer the input signal inverted through the third inverter; A first logic circuit controlled by the inverted clock signals through the first and second inverters to NAND-operate the inverted input signal and the reset signal through the third inverter; A second logic circuit for NAND-operating the reset signal and the input signal transferred through the first transfer gate; A second transmission gate controlled by clock signals inverted through the first and second inverters to transfer the input signal transmitted through the first transmission gate; A fourth inverter for inverting the output of the second logic circuit; A fifth inverter for inverting the output of the second transfer gate; An output terminal connected to current paths formed between an output terminal of the second logic circuit and an input of the fourth inverter, and an output terminal connected to current paths formed between an output terminal of the second transmission gate and an input of the fifth inverter. And a sixth inverter having a sixth inverter. The method of claim 1, The inversion circuit, A first PMOS transistor having one current path and controlled to said input signal; A second PMOS transistor having one current path and controlled to the clock signal inverted through the second inverter; A first NMOS transistor having one current path and controlled to the clock signal inverted through the first inverter; A second NMOS transistor having one current path and controlled to the input signal, The current paths of the transistors are sequentially formed in series between a supply voltage and a ground voltage. The method of claim 1, The first logic means, A first PMOS transistor having a first current electrode, a second current electrode, and a gate controlled to the reset signal; A first current electrode connected to the first current electrode of the first transistor, a second current electrode connected to the second current electrode of the first transistor, and a gate controlled to the clock signal inverted through the third inverter. 2 PMOS transistors; A third PMOS transistor having one current path and controlled to the clock signal inverted through the first inverter; A first NMOS transistor having one current path and controlled to the clock signal inverted through the second inverter; A second NMOS transistor having one current path and controlled to the input signal inverted through the third inverter; A third NMOS transistor having one current path and controlled to the reset signal; And the third PMOS transistor and the first to third NMOS transistors are sequentially formed in series between a second current electrode of the first and second PMOS transistors and the ground voltage.