KR930003293A - MOS transistor manufacturing method - Google Patents

MOS transistor manufacturing method Download PDF

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Publication number
KR930003293A
KR930003293A KR1019910011722A KR910011722A KR930003293A KR 930003293 A KR930003293 A KR 930003293A KR 1019910011722 A KR1019910011722 A KR 1019910011722A KR 910011722 A KR910011722 A KR 910011722A KR 930003293 A KR930003293 A KR 930003293A
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KR
South Korea
Prior art keywords
gate
oxide film
source
mos transistor
forming
Prior art date
Application number
KR1019910011722A
Other languages
Korean (ko)
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KR100192474B1 (en
Inventor
이경수
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910011722A priority Critical patent/KR100192474B1/en
Publication of KR930003293A publication Critical patent/KR930003293A/en
Application granted granted Critical
Publication of KR100192474B1 publication Critical patent/KR100192474B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

모스 트랜지스터 제조방법MOS transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 엔모스 트랜지스터 구조 단면도.2 is a cross-sectional view of an NMOS transistor structure of the present invention.

Claims (1)

기판위에 필드산화막 및 게이트형성이후 진행되는 모스 트랜지스터 제조공정에 있어서, 게이트를 마스크로 저농도 이온을 주입하여 저농도 소오스/드레인 영역을 형성하기 위한 스텝, 전체적으로 열적으로 제1산화막을 얇게 형성시킨후 이어 제2산화막을 소정두께로 증착하고 이 제2산화막을 에치하여 게이트 측벽 산화막을 형성하기 위한 스텝, 전체적으로 언도우프된 폴리실리콘막을 증착하고 이것에 소오스/드레인 영역과 동형의 고농도 이온을 도핑한후 에치하여 소오스/드레인의 콘텍트로 사용될 게이트측벽 폴리실리콘막을 각각 형성하기 위한 스텝, 어닐링을 실시하여 게이트 측벽 폴리실리콘막와 고농도 이온을 기판에 확산시킴으로서 고농도 소오스/드레인을 형성하기 위한 스텝, 절연막을 전체적으로 중착후 포토/에치공정을 거쳐 게이트 상측과 상기 게이트측벽 폴리실리콘막의 상측부위를 제거함으로써 각 콘택트를 형성하기위한 스텝이 차례로 수행되는 것을 특징으로 하는 모스 트랜지스터 제조방법.In the MOS transistor fabrication process that proceeds after the formation of the field oxide film and the gate on the substrate, a step for forming a low concentration source / drain region by implanting low concentration ions using a gate as a mask; Depositing a second oxide film to a predetermined thickness and etching the second oxide film to form a gate sidewall oxide film, and depositing an undoped polysilicon film as a whole, and then doping the source / drain regions and high concentration ions of the same type Steps for forming gate sidewall polysilicon films to be used as source / drain contacts, and annealing to diffuse gate sidewall polysilicon films and high concentration ions onto the substrate to form high concentration source / drain, and after insulating the entire photo Gate through / etch process Side and the MOS transistor manufacturing method as the gate sidewall of the polysilicon film characterized in that the step is performed in order for forming the respective contact by removing the upper portion. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910011722A 1991-07-10 1991-07-10 Method of manufacturing mosfet KR100192474B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011722A KR100192474B1 (en) 1991-07-10 1991-07-10 Method of manufacturing mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011722A KR100192474B1 (en) 1991-07-10 1991-07-10 Method of manufacturing mosfet

Publications (2)

Publication Number Publication Date
KR930003293A true KR930003293A (en) 1993-02-24
KR100192474B1 KR100192474B1 (en) 1999-06-15

Family

ID=19317061

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910011722A KR100192474B1 (en) 1991-07-10 1991-07-10 Method of manufacturing mosfet

Country Status (1)

Country Link
KR (1) KR100192474B1 (en)

Also Published As

Publication number Publication date
KR100192474B1 (en) 1999-06-15

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