KR930002029Y1 - Audio noise removing circuit of vdp - Google Patents

Audio noise removing circuit of vdp Download PDF

Info

Publication number
KR930002029Y1
KR930002029Y1 KR2019870024139U KR870024139U KR930002029Y1 KR 930002029 Y1 KR930002029 Y1 KR 930002029Y1 KR 2019870024139 U KR2019870024139 U KR 2019870024139U KR 870024139 U KR870024139 U KR 870024139U KR 930002029 Y1 KR930002029 Y1 KR 930002029Y1
Authority
KR
South Korea
Prior art keywords
circuit
output
vdp
noise
voice
Prior art date
Application number
KR2019870024139U
Other languages
Korean (ko)
Other versions
KR890014628U (en
Inventor
박승수
Original Assignee
주식회사 금성사
최근선
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사, 최근선 filed Critical 주식회사 금성사
Priority to KR2019870024139U priority Critical patent/KR930002029Y1/en
Publication of KR890014628U publication Critical patent/KR890014628U/en
Application granted granted Critical
Publication of KR930002029Y1 publication Critical patent/KR930002029Y1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/24Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

내용 없음.No content.

Description

VDP의 음성노이즈 제거회로VDP Voice Noise Reduction Circuit

제1도는 본 고안에 따른 회로도.1 is a circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 위상오차 신호단 2 : 미분회로1: Phase error signal stage 2: Differential circuit

3 : 적분회로 4 : 반전 증폭회로3: integrating circuit 4: inverting amplifier circuit

5 : 감산회로 6 : 복조음성 출력단5 subtraction circuit 6 demodulation audio output stage

7 : 음성출력단 IC1: 전압플로워7: Voice output terminal IC 1 : Voltage Follower

IC2, IC3: 연산증폭기 R1~R9: 저항IC 2 , IC 3 : Operational Amplifiers R 1 to R 9 : Resistance

C1~C5: 콘덴서C 1 ~ C 5 : Capacitor

본 고안은 VDP(Video disc plaqer)에 있어서, 신호 프로세싱(processing)에서의 음성노이즈 제거 회로에 관한 것으로, 특히 위상차에 따른 노이즈들을 제거하기에 적당하도록한 VDP의 음성노이즈제거회로에 관한 것이다.The present invention relates to a speech noise canceling circuit in signal processing in a video disc plaqer (VDP), and more particularly to a speech noise canceling circuit of a VDP that is suitable for removing noise due to a phase difference.

종래에는 음성노이즈 제거회로는 스위치 온/오프에 따른 노이즈등은 제거시킬수 있었지만 FM 신호의 위상오차에 따라 발생하는 음성노이즈는 제거시킬수 없어 제품의 품질이 저하되는 등 여러 문제점이 있었다.Conventionally, the voice noise removing circuit has been able to remove noise due to the switch on / off, but there are various problems such as deterioration of the product quality due to the noise noise generated by the phase error of the FM signal.

따라서 상기한 문제점을 개선시키고자 안출한 본 고안은 시간축 오차즉, 위상오차에 따라 발생하는 노이즈를 제거시키고 FM 신호의 모든 노이즈를 방지시켜 양호한 음질을 재생시킬수 있는 VDP의 음성노이즈 제거회로를 제공함에 목적이 있다.Therefore, the present invention devised to improve the above problems provides a noise reduction circuit of VDP capable of reproducing good sound quality by eliminating noise generated by time-base error, that is, phase error, and preventing all noise of the FM signal. There is a purpose.

상기한 목적으로 안출한 본 고안의 회로구성을 제1도에 따라 설명하면 다음과 같다.Referring to Figure 1 the circuit configuration of the present invention devised for the above purpose is as follows.

위상오차신호단(1)은 미분회로(2)의 저항(R1)과 콘덴서(C1)를 차례로 통하여 접지접속한 저항(R2)과 전압 플로워(fllower, IC1)의 정입력단(+)에 각각 연결하고, 상기 전압 프로워(IC1)의 출력단은 저항(R3,R4)과 콘덴서(C2)로 구성된 적분회로(3)를 통하여 연산증폭기(IC2)와 저항(R5) 및 콘덴서(C3)로 구성된 반전중폭회로(4)의 입력단에 연결하며 이의 출력단에는 감산회로(5)의 저항(R6)과 콘덴서(C4) 및 반고정저항(R9)을 차례로 연결하여 연산증폭기(IC3)의 부입력단(-)에 연결한다.The phase error signal stage 1 has a resistor R 2 connected to the ground through the resistor R 1 of the differential circuit 2 and the capacitor C 1 in turn, and the positive input terminal of the voltage follower IC 1 (+). ), And the output terminal of the voltage probe IC 1 is connected to the operational amplifier IC 2 and the resistor R through an integrating circuit 3 composed of resistors R 3 and R 4 and a capacitor C 2 . 5 ) and the input terminal of the inverted amplitude circuit (4) consisting of a condenser (C 3 ), and the output terminal thereof has a resistor (R 6 ), a capacitor (C 4 ), and a semi-fixed resistor (R 9 ) of the subtraction circuit (5). Connect it in turn to the negative input terminal (-) of the operational amplifier (IC 3 ).

또한 복조음성 출력단(6)에는 감산회로(5)의 저항(R7)과 콘덴서(C5)및 반고정저항(R9)을 차례로 연결하여 연산증폭기(IC3)의 부입력단(-)을 연결하고 감산회로(5)의 출력단인 연산증폭기(IC3)의 출력단에 음성출력단(7)을 연결한다.In addition, the negative input terminal (-) of the operational amplifier IC 3 is connected to the demodulation audio output terminal 6 by connecting a resistor R 7 of the subtraction circuit 5, a capacitor C 5 , and a semi-fixed resistor R 9 . The voice output terminal 7 is connected to the output terminal of the operational amplifier IC 3, which is an output terminal of the subtraction circuit 5.

이와같이 구성한 본 고안의 동작설명을 제1도에 의거 설명하면 다음과 같다.When explaining the operation of the present invention configured in this manner based on Figure 1 as follows.

위상오차신호단(1)에서 출력된 신호는 미분회로(2)를 통하여 전압플로워(IC1)에서 임피던스가 변환되고 적분회로(3)의 저항(R3,R4)과 콘덴서(C2)에 의해 1KHz이상의 노이즈 성분에 대해서는 연산증폭기(IC2)와 저항(R5) 및 콘덴서(C3)로 구성한 반전 증폭회로(4)에서 노이즈를 인버팅시켜서 감산회로(5)에 입력된다.The signal output from the phase error signal stage 1 is converted into an impedance in the voltage follower IC 1 through the differential circuit 2, and the resistors R 3 and R 4 and the capacitor C 2 of the integrated circuit 3 are converted. Therefore, the noise component of 1 KH z or more is inputted to the subtraction circuit 5 by inverting the noise in the inverted amplifier circuit 4 composed of the operational amplifier IC 2 , the resistor R 5 , and the capacitor C 3 .

이때 복조음성출력단(6)에서 출력된 음성복조 출력도 감산회로(5)에 입력되어 신호와 합쳐지면 결국 음성복조 출력에 포함된 각종 노이즈를 감산회로(5)에서 감산시키므로 음성신호의 노이즈는 제거된 다음 이 신호를 연산증폭기(IC3)로 증폭하여 음성출력단(7)으로 출력시킨다.At this time, the voice demodulation output output from the demodulation voice output stage 6 is also input to the subtraction circuit 5 and merged with the signal, thereby subtracting various noises included in the voice demodulation output in the subtraction circuit 5, thereby eliminating the noise of the voice signal. Then, this signal is amplified by the operational amplifier IC 3 and output to the voice output terminal 7.

이와 같이 본 고안은 위상오차에 따른 노이즈가지 완벽하게 제거시킬 수 있기 때문에 양호한 음질을 재생할 수 있는 것에 효과가 있다.As such, the present invention is effective in reproducing a good sound quality because the noise due to the phase error can be completely removed.

Claims (1)

VDP의 음성출력 회로에 있어서, 위상오차 신호(1)를 미분하는 미분회로(2)와, 상기 미분회로(2)의 출력을 임피던스 변환하는 전압플로워(IC1)와, 상기 전압플로워(IC1)의 출력에서 1KHZ이하의 음성 노이즈를 제거하는 적분회로(3)와, 상기 적분회로(3)에서 출력되는 1KHZ 이상의 노이즈 성분을 반전시켜 증폭하는 반전 증폭회로(4)와, 복조음성 출력(6)으로 부터 상기 반전증폭회로(4)의 출력을 감산시킴으로써 음성복조 출력에 포함된 각종 노이즈를 제거하는 감산회로(5)를 포함하여 구성된 것을 특징으로 하는 VDP의 음성노이즈 제거회로.In the audio output circuit of the VDP, a differential circuit 2 for differentiating a phase error signal 1, a voltage follower IC1 for impedance-converting the output of the differential circuit 2, and a voltage follower IC1. An integrating circuit 3 for removing 1 KHZ or less of voice noise from the output, an inverting amplifying circuit 4 for inverting and amplifying noise components of 1 KHZ or more output from the integrating circuit 3, and a demodulation sound output 6 And a subtraction circuit (5) for removing various noises included in the voice demodulation output by subtracting the output of the inversion amplifier circuit (4).
KR2019870024139U 1987-12-31 1987-12-31 Audio noise removing circuit of vdp KR930002029Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870024139U KR930002029Y1 (en) 1987-12-31 1987-12-31 Audio noise removing circuit of vdp

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870024139U KR930002029Y1 (en) 1987-12-31 1987-12-31 Audio noise removing circuit of vdp

Publications (2)

Publication Number Publication Date
KR890014628U KR890014628U (en) 1989-08-11
KR930002029Y1 true KR930002029Y1 (en) 1993-04-23

Family

ID=19271163

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019870024139U KR930002029Y1 (en) 1987-12-31 1987-12-31 Audio noise removing circuit of vdp

Country Status (1)

Country Link
KR (1) KR930002029Y1 (en)

Also Published As

Publication number Publication date
KR890014628U (en) 1989-08-11

Similar Documents

Publication Publication Date Title
JPS56132804A (en) Operational tone quality control circuit
KR860007660A (en) Noise reduction circuit
KR930002029Y1 (en) Audio noise removing circuit of vdp
US5343197A (en) Digital-to-analog converter
JPS57120207A (en) Reproducing device for multiple-recorded information
KR890008428Y1 (en) High frequency noise cut circuit
KR950019712A (en) Infrared sensor driving circuit
KR930004524Y1 (en) Data audio noise removing circuit of cd-rom
KR910009467B1 (en) Auclio signal removing device
JPS55110427A (en) Clamp circuit
JPS57172511A (en) Time-axis compressing and expanding circuit
KR900003542Y1 (en) Noise minimising circuit of reproduce white signal
JPS607572Y2 (en) Pulse noise signal reduction device
KR890005820Y1 (en) Audio switching circuits of hifi vtr
KR900008896Y1 (en) Noise reduction circuit for the tape of part without signal
JPH0727706Y2 (en) Audio playback circuit
JPS6110327A (en) Pulse noise eliminating circuit
JPS6430071A (en) Reproducing circuit for digital optical disk
JPS5669925A (en) Digital processing system
KR900010832Y1 (en) Mic noise removing circuit
JPH0413857Y2 (en)
JPS5926673Y2 (en) Noise removal circuit
KR940003920Y1 (en) Click noise preventing apparatus of digital audio device
KR940000507Y1 (en) Agc for special frequency signal
KR920002928Y1 (en) Voice lowpass expanding circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19951226

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee