KR930001902B1 - Manufacturing method of ldd - Google Patents

Manufacturing method of ldd Download PDF

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KR930001902B1
KR930001902B1 KR1019900012446A KR900012446A KR930001902B1 KR 930001902 B1 KR930001902 B1 KR 930001902B1 KR 1019900012446 A KR1019900012446 A KR 1019900012446A KR 900012446 A KR900012446 A KR 900012446A KR 930001902 B1 KR930001902 B1 KR 930001902B1
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gate
region
channel
field
forming
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KR1019900012446A
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Korean (ko)
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KR920005392A (en
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구정석
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

The method for prepring LDD (lightly doped drain) comprises (a) forming base oxide and nitride (4) on the P-type semiconductor substrate (1), (b) removing nitride (4) of field and channel regions and implanting ions into the field region, (c) growing oxide (3) on the nitride-removed part and forming low conc. N-type source/drain region (15) by removing nitride (4), (d) removing field oxide (3) of channel region and implanting ions for threshold voltage control, (e) growing gate oxide (17) and forming gate (18) on the channel and source/drain regions, and (f) forming high conc. N-type source/drain region (10) on the substrate (10) using gate (18) as a mask.

Description

LDD 제조방법LDD Manufacturing Method

제1a도-제1d도는 종래의 LDD 제조공정도.1A-1D are conventional LDD manufacturing process diagrams.

제2a도-제2f도는 본 발명에 따른 LDD 제조공정도.2a to 2f are LDD manufacturing process according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 필드도우핑영역1 silicon substrate 2 field doping region

3 : 필드산화막 4 : 질화막3: field oxide film 4: nitride film

15 : 저농도 n형 소오스/드레인영역15: low concentration n-type source / drain region

16 : 채널 도우핑영역 17 : 산화막16 channel doping region 17 oxide film

18 : 게이트 19, 20 : 포토레지스트18 gate 19, 20 photoresist

10 : 고농도 n형 소오스/드레인영역10: high concentration n-type source / drain region

본 발명은 LDD(Ligwtly doped drain) 제조방법에 관한 것으로, 특히 LDD의 수명개선 및 비대칭 특성향상 및 제조공정의 단순화에 적당하도록 한 LDD 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a ligwtly doped drain (LDD), and more particularly, to an LDD manufacturing method which is suitable for improving the lifetime and asymmetric characteristics of the LDD and simplifying the manufacturing process.

종래의 LDD 제조방법에 대해 제1도의 공정도를 통해 상세히 설명하면 다음과 같다.The conventional LDD manufacturing method will be described in detail with reference to the process diagram of FIG.

먼저 제1a도에서와 같이 P형 실리콘 기판(1)에 열산화막을 성장시키고, 질화막(Nitride)(4)를 디포지션 한 후 필드산화막과 채널 영역이 형성되어야 할 부분의 질화막(4)을 에치하고, 그 다음 새로운 마스크를 사용하여 필드영역에 채널스톱(Chanel stop) 이온주입(필드 도우핑영역(2) 형성)을 한 후 열처리공정으로 필드영역과 채널영역을 산화하여 필드산화막(3)을 형성한다.First, as shown in FIG. 1A, a thermal oxide film is grown on the P-type silicon substrate 1, the nitride film 4 is deposited, and the nitride film 4 of the portion where the field oxide film and the channel region should be formed is etched. Then, channel stop ion implantation (field doping region 2 formation) is performed in the field region using a new mask, and then the field oxide layer 3 is oxidized by annealing. Form.

그 다음 제1b도에서와 같이 질화막(4)을 제거하고 채널이 될 부분의 필드산화막(3)을 에치하고서 문턱전압(thrcshold voltape) 이온주입을 실시한 다음 게이트 산화막(5)을 성장시키고 다결정 실리콘을 적층 및 패터닝 하여 게이트(6)를 형성하고, 그 다음엔 n형 저농도 불순물 이온을 주입하여 저농도 n형 소오스/드레인 영역을 형성한다.Then, as shown in FIG. 1B, the nitride film 4 is removed, the field oxide film 3 of the channel portion is etched, the threshold voltage ion implantation is performed, the gate oxide film 5 is grown, and the polycrystalline silicon is grown. The gate 6 is formed by lamination and patterning, and then n-type low concentration impurity ions are implanted to form a low concentration n-type source / drain region.

그리고 제1c도에서와 같이 게이트(6) 측벽에 절연막으로 사이드월(8)을 형성한 후 n형 고농도 불순물이온 주입하여 고농도 n형 소오스/드레인 영역(9)을 형성한다.As shown in FIG. 1C, the sidewalls 8 are formed on the sidewalls of the gate 6 as an insulating film, and then the n-type high concentration impurity ions are implanted to form the high concentration n-type source / drain regions 9.

그런데 상기와 같이 형성된 종래의 LDD 구조(제1d도)에 있어서는 채널길이가 게이트에 의해 결정되므로 LDD의 수명개선 및 비대칭 특성을 향상시키기 위해서는 게이트 에지(Gate Edge)가 채널쪽에 있는 버즈빅(Bird's Beak) 자리보다 바깥에 있어야 한다.However, in the conventional LDD structure (FIG. 1d) formed as described above, since the channel length is determined by the gate, in order to improve the lifespan and asymmetry of the LDD, the gate edge is the Bird's Beak on the channel side. Must be outside the seat.

그런데 일반적으로 버즈빅(Bird's Beak)을 고려해 볼 때 채널이 형성될 자리의 필드 옥사이드를 디파인(Define)하는 것이 몹시 어려운 단점이 있었다(예 : 게이트가 1.0㎛이고 필드옥사이드의 두께가 5000Å 정도이면 버즈빅이 양쪽 합쳐서 0.1㎛이상이 되므로 질화막 스페이싱(Spacing)이 0.3㎛이하가 되지 않으면 안된다).However, in general, considering the Bird's Beak, it is very difficult to define the field oxide where the channel is to be formed (e.g., when the gate is 1.0 μm and the thickness of the field oxide is about 5000Å, Since both of the BICs are 0.1 µm or more in total, the nitride film spacing must be 0.3 µm or less).

본 발명은 이러한 단점을 해결하기 위해 안출된 것으로 첨부도면을 참조하여 상세히 설명하면 다음과 같다.The present invention has been made to solve the above disadvantages and will be described in detail with reference to the accompanying drawings.

먼저 P형 실리콘 기판(1) 위에 제2a도에서와 같이 LOCOS(Local Oxidation of silicon)방법으로 필드산화막(3)을 만든다.First, the field oxide film 3 is formed on the P-type silicon substrate 1 by the LOCOS (Local Oxidation of Silicon) method as shown in FIG. 2A.

베이스 산화막을 성장하고 나이트 라이드(4)를 디포지션 한 뒤 마스크를 써서 필드영역(격리영역)과 채널영역 질화막(4)을 식각한 다음 또 다른 마스크를 사용하여 필드영역에 채널스톱 이온을 주입하여 필드도우핑영역(2)을 형성하고 열처리로 산화하여 필드산화막(3)을 형성한다.After growing the base oxide layer and depositing the nitride (4), the field region (isolation region) and the channel region nitride film 4 are etched using a mask, and then channel stop ions are implanted into the field region using another mask. The field doped region 2 is formed and oxidized by heat treatment to form the field oxide film 3.

그 다음 제2b도에서와 같이 질화막(4)을 제거하고 n형 저농도 불순물 이온을 주입하여 저농도 n형 소오스/드레인 영역(15)을 만들어 준 후 제2c도에서와 같이 포토레지스트(19)를 사용하여 필드산화막(3) 중에 채널이 될 부분을 식각해 낸 후 제2d도와 같이 문턱전압을 조절하기 위한 채널(VTN) 이온을 주입하여 채널 도우핑영역(16)을 형성한 다음 열산화하여 게이트 산화막(17)을 적당한 두께로 기르고 포토레지스트(19)를 제거한 뒤 다결정 실리콘과 포토레지스트(20)를 증착하고 게이트 마스크를 써서 노광하여 포토레지스트(20) 마스크를 정의하여 다결정 실리콘을 식각하여 게이트(18)를 형성한다.Next, as shown in FIG. 2B, the nitride film 4 is removed and the n-type low concentration impurity ions are implanted to form a low concentration n-type source / drain region 15. Then, the photoresist 19 is used as shown in FIG. 2C. After etching the portion of the field oxide film 3 to be a channel, the channel doping region 16 is formed by implanting channel (VTN) ions for adjusting the threshold voltage as shown in FIG. 2d and then thermally oxidizing the gate oxide film. The photoresist 20 is grown to an appropriate thickness, the photoresist 19 is removed, the polycrystalline silicon and the photoresist 20 are deposited, and then exposed using a gate mask to define a photoresist 20 mask to etch the polycrystalline silicon to form a gate 18. ).

이때 게이트(18)는 경신식각을 사용하여 사다리꼴로 만든다.At this time, the gate 18 is trapezoidal by using a renewal etching.

또한 게이트는 채널자리에 있던 필드산화막의 길이보다 길게 만든다.In addition, the gate is made longer than the length of the field oxide film in the channel position.

그 다음 제2e도에서와 같이 포토레지스트(20)를 제거하고 n형 고농도 불순물 이온주입하여 고농도 n형 소오스/드레인 영역(10)을 형성하면 제2f도와 같은 LDD 구조의 소오스/드레인 영역이 된다.Then, as shown in FIG. 2E, when the photoresist 20 is removed and the n-type high concentration impurity ion implantation is performed to form the high concentration n-type source / drain region 10, the source / drain region of the LDD structure as shown in FIG. 2f is formed.

따라서 본 발명은 채널길이가 게이트 길이가 아닌 필드길이에 의해 결정되므로 질화막 스페이스를 종전디자인룰과 같게 하여 적용할 수 있고 소오스/드레인과 게이트 오버랩(Gate Overlap) 길이를 자유롭게 조절할 수 있게 됨에 따라 게이트와 고농도 n형 소오스/드레인이 오버랩 되므로 핫캐리어(Hot Carrier) 특성 및 성능(Performance)이 향상되면, 필드산화막이 있는 상태에서 저농도 n형 불순물 이온을 주입하게 되고 또 사이드월을 쓰지 않으므로 게이트를 경신식각할 수 있게 되어 LDD의 비대칭 특성을 최소화 할 수 있는 효과가 있다.Therefore, in the present invention, the channel length is determined by the field length, not the gate length, so that the nitride film space can be applied as the previous design rule, and the source / drain and gate overlap lengths can be freely adjusted. When the high concentration n-type source / drain is overlapped, the hot carrier characteristics and performance are improved, so that the low concentration n-type impurity ions are implanted in the presence of the field oxide layer and the gate is not etched because sidewalls are not used. It is possible to minimize the asymmetrical characteristics of the LDD.

Claims (3)

P형 반도체 기판(1) 위에 베이스 산화막과 질화막(4)을 순차적으로 형성하는 공정과, 필드영역과 채널영역의 질화막(4)을 제거하고 필드영역에 채널스톱 이온주입하는 공정과, 질화막(4)이 제거된 부위에 필드산화막(3)을 성장하고 질화막(4)을 제거하여 저농도 n형 소오스/드레인 영역(15)을 형성하는 공정과, 채널영역의 필드산화막(3)을 제거하고 문턱전압 조절용 이온주입하는 공정과, 게이트 산화막(17)을 성장하고 채널영역과 저농도 n형 소오스/드레인 영역의 소정부위에 걸쳐 게이트(18)을 형성하는 공정과, 게이트(18)을 마스크로 하여 기판(1)에 고농도 n형 소오스/드레인 영역(10)을 형성하는 공정을 포함함을 특징으로 하는 LDD 제조방법.A step of sequentially forming the base oxide film and the nitride film 4 on the P-type semiconductor substrate 1, removing the nitride film 4 in the field region and the channel region, and implanting channel stop ions into the field region, and the nitride film 4 Growing the field oxide film 3 at the portion where the c) is removed and forming the low concentration n-type source / drain region 15 by removing the nitride film 4, and removing the field oxide film 3 in the channel region and removing the threshold voltage. A process of implanting a control ion implantation, growing a gate oxide film 17 to form a gate 18 over a predetermined region of a channel region and a low concentration n-type source / drain region, and using the substrate 18 as a mask 1) forming a high concentration n-type source / drain region (10). 제1항에 있어서, 게이트(18) 형성시 경사에치하여 게이트의 상부보다 하부를 길게 형성함을 특징으로 하는 LDD 제조방법.The method of claim 1, wherein the lower portion is formed longer than the upper portion of the gate by the inclined etch when forming the gate (18). 제1항에 있어서, 게이트(18)와 고농도 n형 소오스/드레인 영역의 일부가 중첩되도록 형성함을 특징으로 하는 LDD 제조방법.2. The method of claim 1, wherein the gate (18) and a portion of the high concentration n-type source / drain region overlap each other.
KR1019900012446A 1990-08-13 1990-08-13 Manufacturing method of ldd KR930001902B1 (en)

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KR930001902B1 true KR930001902B1 (en) 1993-03-19

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