KR930001431A - DRAM Cell Structure and Manufacturing Method - Google Patents

Abstract

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Description

DRAM Cell Structure and Manufacturing Method

Since this is an open matter, no full text was included.

1 is a cross-sectional view of a DRAM cell process of the present invention.

2 is a cross-sectional view of a conventional DRAM cell process.

* Explanation of symbols for main parts of the drawings

1: p ⁺ substrate 2: capacitor dielectric

3: n ⁺ polysilicon 4: epi layer

5: gate oxide film 6: polysilicon

7: CVD oxide film 8: bit line

Claims (3)

Forming a capacitor by forming a capacitor dielectric (2) and n ⁺ polysilicon (3) in the trench formed in the P ⁺ substrate (1), and forming a source and a drain perpendicular to the n ⁺ polysilicon (3) In addition, the structure of the DRAM cell formed by forming a gate on the side walls of the source and drain. forming a trench on a p ⁺ substrate (1) and capacitors comprising the steps of jeungpak the dielectric (2), filling up the trench, n ⁺ polysilicon (3) etch-back by removing the capacitor dielectric (2) on top of the substrate (1) After depositing an oxide film on the entire surface and selectively etching by a masting process, growing an epitaxial layer 4 on the etched portion, implanting n ⁺ ions, removing the oxide film, and then forming a gate oxide film 5 A step of depositing and etching back the polysilicon 6 to form a sidewall gate, and a step of depositing the CVD oxide film 7 and opening the bit line contact and then forming the bit line 8. A method for producing a DRAM cell. The method of claim 2. Using the n ⁺ substrate instead of the substrate P ⁺ and n ⁺ polysilicon instead of the method of producing a di raemsel using the P ⁺ polysilicon. ※ Note: The disclosure is based on the initial application.