KR920022445A - Metal wiring film formation method - Google Patents

Metal wiring film formation method Download PDF

Info

Publication number
KR920022445A
KR920022445A KR1019910008122A KR910008122A KR920022445A KR 920022445 A KR920022445 A KR 920022445A KR 1019910008122 A KR1019910008122 A KR 1019910008122A KR 910008122 A KR910008122 A KR 910008122A KR 920022445 A KR920022445 A KR 920022445A
Authority
KR
South Korea
Prior art keywords
amorphous silicon
forming
silicon layer
wiring film
contact hole
Prior art date
Application number
KR1019910008122A
Other languages
Korean (ko)
Other versions
KR950000847B1 (en
Inventor
진유찬
이정규
김범수
장근하
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910008122A priority Critical patent/KR950000847B1/en
Publication of KR920022445A publication Critical patent/KR920022445A/en
Application granted granted Critical
Publication of KR950000847B1 publication Critical patent/KR950000847B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.No content.

Description

금속 배선막 형성 방법Metal wiring film formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명에 따른 금속배선막 형성방법의 일 실시예를 나타낸 공정순서도.2A to 2F are process flowcharts showing one embodiment of a method for forming a metal wiring film according to the present invention.

Claims (15)

금속배선막 형성방법에 있어서, 반도체기판상의 절연층에 형성된 콘택트 홀을 비정질실리콘으로 매립하여 플러그를 형성한 후 금속배선막을 형성하는 것을 특징으로 하는 금속배선막 형성방법.A method for forming a metal wiring film, the method comprising: forming a plug after filling a contact hole formed in an insulating layer on a semiconductor substrate with amorphous silicon to form a plug, and then forming a metal wiring film. 제1항에 있어서, 상기 콘택트 홀은 그 어스펙트비가 1.5이상이 되도록 형성되는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 1, wherein the contact hole is formed so that its aspect ratio is 1.5 or more. 제2항에 있어서, 상기 플러그의 형성은 상기 콘택트 홀 형성 후에 제1비정질실리콘층을 형성하는 공정과, 상기 제1비정질실리콘층에 불순물을 주입하는 공정과, 상기 불순물 주입 공정후 상기 콘택트 홀이 채워지도록 상기 제1비정질실리콘층 위에 제2비정질실리콘층을 형성하는 공정과, 상기 제2비정질실리콘층에 불순물을 주입하는 공정과, 상기 제1및 제2비정질실리콘층을 에치 백하여 상기 콘택트 홀내에만 비정질실리콘을 남기는 공정으로 이루어지는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 2, wherein the forming of the plug comprises: forming a first amorphous silicon layer after the contact hole is formed; Forming a second amorphous silicon layer on the first amorphous silicon layer to be filled; implanting impurities into the second amorphous silicon layer; and etching back the first and second amorphous silicon layers to form the contact hole. A method for forming a metal wiring film, comprising the step of leaving amorphous silicon inside. 제3항에 있어서, 상기 제1비정질실리콘층은 저압화학기상성장 장치를 이용하여 550℃에서 500Å∼2000Å 정도의 두께로 형성됨을 특징으로 하는 금속배선막 형성방법.The method of claim 3, wherein the first amorphous silicon layer is formed to a thickness of about 500 kPa to about 2000 kPa at 550 ° C. using a low pressure chemical vapor growth apparatus. 제4항에 있어서, 상기 제1비정질실리콘층에 불순물을 주입하는 공정은 에너지와 도우스를 달리하여 2회 실시하는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 4, wherein the implanting the impurity into the first amorphous silicon layer is performed twice with different energy and dose. 제5항에 있어서, 상기 2회 실시하는 불순물 주입 공정중에서, 그 첫번째 불순물주입은 30-60keV의 에너지로 5×1015~5×1016이온/cm2의 인을, 그 두 번째 불순을 주입은 80∼150keV의 에너지로 1×1015∼5×1515이온/cm2의 인을 각각 이온주입하여 이루어지는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 5, wherein in the second impurity implantation process, the first impurity implantation is implanted with phosphorus of 5 × 10 15 to 5 × 10 16 ions / cm 2 at an energy of 30-60 keV and the second impurity. A method for forming a metal wiring film, characterized in that the ion is implanted with phosphorus of 1 × 10 15 to 5 × 15 15 ions / cm 2 at an energy of 80 to 150 keV. 제6항에 있어서, 상기 제2비정질실리콘층은 저압화학기상성장 장치를 이용하여 550℃에서 1500Å-5500Å 정도의 두께로 형성됨을 특징으로 하는 금속배선막 형성방법.7. The method of claim 6, wherein the second amorphous silicon layer is formed to a thickness of about 1500Å-5500Å at 550 ° C using a low pressure chemical vapor growth apparatus. 제7항에 있어서, 상기 제2비정질실리콘층에 불순물을 주입하는 공정은 50-150keV의 에너지로 1×1015~5×1016이온/cm2의 인을 이온주입하여 이루어지는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 7, wherein the implanting the impurity into the second amorphous silicon layer is performed by ion implanting phosphorus of 1 × 10 15 to 5 × 10 16 ions / cm 2 with an energy of 50-150 keV. Wiring film formation method. 제8항에 있어서, 상기 금속배선막은 상기 비정질실리콘 플러그 형성 후에 금속장벽층과 금속층을 차례로 형성하여 이루어지는 것을 특징으로 하는 금속배선막 형성방법.9. The method of claim 8, wherein the metal wiring film is formed by sequentially forming a metal barrier layer and a metal layer after the amorphous silicon plug is formed. 반도체기판상에 절연층을 형성하는 공정 ; 상기 절연충에 콘택트 홀을 형성하는 공정; 상기 공정들을 통하여 얻어진 전체 표면상에 제1비정질실리콘층을 형성하는 공정; 상기 제1비정질실리콘층에 에너지와 도우스를 달리하여 불순물을 2회 주입하는 공정 ; 상기 2회 불순물 주입 공정후에 상기 콘택트 홀이 채워지도록 상기 제1비정질실리콘층 위에 제2비정질실리콘층을 형성하는 공정; 상기 제2비정질실리콘층에 불순물을 주입하는 공정; 상기 제1및 제2비정질실리콘층을 에치 백하여 상기 콘택트 홀내에만 비정질실리콘 플러그를 남기는 공정; 그리고 상기 비정질실리콘 플러그 형성후 노출된 전체 표면상에 금속배선막을 형성하는 공정으로 이루어지는 것을 특징으로 하는 금속배선막 형성방법.Forming an insulating layer on the semiconductor substrate; Forming a contact hole in the insulating worm; Forming a first amorphous silicon layer on the entire surface obtained through the steps; Implanting impurities twice into the first amorphous silicon layer by varying energy and dose; Forming a second amorphous silicon layer on the first amorphous silicon layer to fill the contact hole after the second impurity implantation process; Implanting impurities into the second amorphous silicon layer; Etching back the first and second amorphous silicon layers to leave an amorphous silicon plug only in the contact hole; And forming a metal wiring film on the entire exposed surface after the amorphous silicon plug is formed. 제10항에 있어서, 상기 콘택트 홀은 그 어스펙트비가 1.5이상이 되도륵 형성되는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 10, wherein the contact hole is formed even if its aspect ratio is 1.5 or more. 제11항에 있어서, 상기 제1비정질실리콘층은 저압화학기상성장장치를 이용하여 550℃에서 500Å∼2000Å 정도의 두께로 형성됨을 특징으로 하는 금속배선막 형성방법.The method of claim 11, wherein the first amorphous silicon layer is formed to a thickness of about 500 kPa to about 2000 kPa at 550 ° C. using a low pressure chemical vapor growth apparatus. 제12항에 있어서, 상기 2회 실시하는 불순물 주입 공정에서, 그 첫번째 불순물주입은 30~60keV의 에너지로 5×1015~5×1016이온/cm2의 인을, 그 두번째 불순물 주입은 80~150keV의 에너지로 1×1015∼5×1515이온/cm2의 인을 각각 이온주입하여 이루어지는 것을 특징으로 하는 금속배선막 형성방법.The method of claim 12, wherein in the second impurity implantation step, the first impurity implantation is 5 × 10 15 to 5 × 10 16 ions / cm 2 of phosphorus at an energy of 30 to 60 keV, and the second impurity implantation is 80 A method for forming a metal interconnection film comprising ion implantation of phosphorus of 1 × 10 15 to 5 × 15 15 ions / cm 2 with an energy of ˜150 keV, respectively. 제13항에 있어서, 상기 제2비정질실리콘층은 저압화학기상성장 장치를 이용하여 550℃에서 1500Å-5500Å 정도의 두께로 형성됨을 특징으로 하는 금속배선막 형성방법.15. The method of claim 13, wherein the second amorphous silicon layer is formed to a thickness of about 1500Å-5500Å at 550 ° C using a low pressure chemical vapor growth apparatus. 제14항에 있어서, 상기 제2비정질실리콘층에 불순물을 주입하는 공정은 50~150keV의 에너지로 1×1015~5×1015이온/cm2의 인을 이온주입하여 이루어지는 것을 특징으로 하는 금속배선막 형성방법. 15. The metal of claim 14, wherein the impurity is implanted into the second amorphous silicon layer by ion implantation of 1 × 10 15 to 5 × 10 15 ions / cm 2 with energy of 50 to 150 keV. Wiring film formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910008122A 1991-05-18 1991-05-18 Forming method of metal wiring film KR950000847B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910008122A KR950000847B1 (en) 1991-05-18 1991-05-18 Forming method of metal wiring film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910008122A KR950000847B1 (en) 1991-05-18 1991-05-18 Forming method of metal wiring film

Publications (2)

Publication Number Publication Date
KR920022445A true KR920022445A (en) 1992-12-19
KR950000847B1 KR950000847B1 (en) 1995-02-02

Family

ID=19314650

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910008122A KR950000847B1 (en) 1991-05-18 1991-05-18 Forming method of metal wiring film

Country Status (1)

Country Link
KR (1) KR950000847B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472722B1 (en) * 1999-06-30 2005-03-07 주식회사 하이닉스반도체 Method for forming line and plug metal wire capable of reducing damage of under layer
KR100537193B1 (en) * 2000-08-31 2005-12-16 주식회사 하이닉스반도체 Method for manufacturing capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472722B1 (en) * 1999-06-30 2005-03-07 주식회사 하이닉스반도체 Method for forming line and plug metal wire capable of reducing damage of under layer
KR100537193B1 (en) * 2000-08-31 2005-12-16 주식회사 하이닉스반도체 Method for manufacturing capacitor

Also Published As

Publication number Publication date
KR950000847B1 (en) 1995-02-02

Similar Documents

Publication Publication Date Title
JP2706469B2 (en) Method for manufacturing semiconductor device
KR980006037A (en) Trench device isolation method for semiconductor devices
US4016007A (en) Method for fabricating a silicon device utilizing ion-implantation and selective oxidation
GB2349505B (en) Method of fabricating a semiconductor device
KR930009023A (en) Contact filling method by two-step deposition of selective tungsten thin film
KR920022445A (en) Metal wiring film formation method
US3810795A (en) Method for making self-aligning structure for charge-coupled and bucket brigade devices
JPS57155765A (en) Manufacture of semiconductor device
US7045417B2 (en) Method of manufacturing semiconductor device
KR100426492B1 (en) Method for forming charge storage electrode of semiconductor device
JPS63236317A (en) Manufacture of semiconductor device
KR920015539A (en) Single poly ypyrom cells and manufacturing method
KR0147486B1 (en) Method for forming contact hole
US5696004A (en) Method of producing semiconductor device with a buried layer
JPH05166943A (en) Manufacture of semiconductor device
KR960015794A (en) Semiconductor device manufacturing method
KR950021093A (en) Metal contact formation method of semiconductor device
KR940009595B1 (en) Forming method of metal wiring film
KR100215829B1 (en) Forming method for tungsten plug
JP2925936B2 (en) Method for manufacturing semiconductor memory device
JPH01243526A (en) Manufacture of semiconductor device
KR920020705A (en) Device Separation Method of Semiconductor Device
JPS6442175A (en) Manufacture of semiconductor device
JPH04208523A (en) Manufacture of semiconductor device
JPH0719779B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060105

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee