JPH05166943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the necessity of separately performing a doping to base diffused layers according to a difference between the conductivity types of the base diffused layers and to form contacts, which have a high aspect ratio, but are low in resistance. CONSTITUTION:A P-type diffused layer 2, an N-type diffused layer 3 and an element isolation region 4 are formed in and on an Si substrate 1. Contact holes 6 and 7 are respectively formed on the layers 2 and 3. A Ti film 8 is deposited on this surface, the holes 6 and 7 are filled with an amorphous silicon film 13, an annealing is performed to activate a dopant and amorphous silicon plugs are changed into N-type polycrystalline silicon plugs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact having a high aspect ratio with a low resistance.

[0002]

2. Description of the Related Art Along with the miniaturization of semiconductor devices, the aspect ratio of contact holes is increasing. In semiconductor devices of the half micron level, in order to compensate for the poor coverage of aluminum wiring, wiring materials are embedded inside the contact holes. In need of technology. One of the embedding techniques is an embedding method using polycrystalline silicon. When this method is carried out, polycrystalline silicon is doped to make it conductive so as to form a contact. In order to obtain good contact characteristics with this method of burying with polycrystalline silicon, it is necessary to form a contact of the same conductivity type as the underlying diffusion layer, that is, a polycrystalline silicon plug, when doping the polycrystalline silicon. .. For example, phosphorus is implanted so that polycrystalline silicon becomes n-type polycrystalline silicon in the n-type diffusion layer, and boron is implanted so that it becomes p-type in the p-type diffusion layer.

Further, since boron used for doping polycrystalline silicon on the p-type diffusion layer forms clusters, the diffusion of boron is suppressed during activation annealing and is not evenly distributed over the entire contact. In addition, phosphorus in the interlayer insulating film around the contact during activation annealing
Diffusion into the contact, and for these reasons, the formed contact having a high aspect ratio has a problem of high resistance.

In order to solve such a problem, there are the following methods (Semiconductor World, 1990, 11, P.
229−P.233 “Low resistance technology for Poly-Si plugs”). 1 and 2 are schematic cross-sectional views showing a step of filling a contact hole with polycrystalline silicon. As shown in FIG. 1A, a p-type diffusion layer 2, an n-type diffusion layer 3,
And element isolation regions 4 are formed. Insulating films SiO _2, 5, 5 are deposited on this surface, and contact holes 6, 7 are formed on the p-type diffusion layer 2 and the n-type diffusion layer 3, respectively.

Then, a polysilicon film 10 is deposited to 100 nm on this surface by a sputtering method. Next, as shown in FIG. 1B, the contact hole 7 is filled and a resist 15 is deposited on the n-type diffusion layer 3. Using this resist 15 as a mask, ⁴⁹ BF ₂ ⁺ is obliquely implanted into the contact hole 6 (1 × 10 ¹⁶ cm ⁻² ions twice), boron is implanted into the side wall in the contact hole 6, and p-type polysilicon is then implanted. The film 11 is formed. After removing the resist 15, polycrystalline silicon 12 is deposited on the polysilicon film 10 and the p-type polysilicon film 11 by the CVD method as shown in FIG. 1 (c).

Then, as shown in FIG. 1D, the entire surface is etched back using the reactive ion etching method to form an insulating film.
The upper portions of SiO _2, 5, 5 and 5 are removed, and polycrystalline silicon plugs 60 and 70 are formed in the contact holes. Figure 2 (e)
As shown in, the polycrystal silicon plug 60 is masked with a resist 15 and the polycrystal silicon plug 70 is filled with ³¹ P ⁺ 1.5 × 10 5.
¹⁶ cm ^-2 ions are implanted to form an n-type polycrystalline silicon plug 71.

Next, as shown in FIG. 2 (f), the resist 15 is removed, the polycrystalline silicon plug 71 is masked with the resist 15, and the p-type polycrystalline silicon plug 60 is filled with ¹¹ B ⁺ 2 × 10 ¹⁶ cm 2.
^-2 ion implantation is performed to form a p-type polycrystalline silicon plug 61. After removing the resist 15 and performing activation annealing, a metal wiring 9 is formed as shown in FIG. 2 (g) and sintering is performed. In the p-type polycrystalline silicon plug 61 thus formed, the side wall and the bottom portion have a higher boron concentration than the inside. Therefore, phosphorus is less likely to diffuse from the interlayer insulating film on the side wall, and the phenomenon of lower carrier concentration is less likely to occur, so that the resistance of the p-type contact is reduced.

[0008]

The contact forming method described above can reduce the resistance of a contact having a high aspect ratio. However, the process is long and complicated because it is necessary to separate the doping due to the difference in the type of the underlying diffusion layer, and it is necessary to perform ion implantation twice in order to lower the contact resistance with the p-type diffusion layer. .. The present invention has been made in view of the above circumstances, and a method for manufacturing a semiconductor, in which it is not necessary to separately perform doping due to the difference in the type of the underlying diffusion layer, and a contact with low resistance is formed even if the aspect ratio is high. The purpose is to provide.

[0009]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which polycrystalline silicon is buried in a contact hole connected to a diffusion layer to form a contact, and the contact hole is made of metal. A thin film is deposited, and n-type polycrystalline silicon is embedded on the surface of the thin film to form a contact.

[0010]

In the method of manufacturing a semiconductor device according to the present invention, the metal thin film is deposited in the contact hole and the n-type polycrystalline silicon is embedded in the surface of the contact hole.
The n-type polycrystalline silicon can be used for the contact of the p-type diffusion layer without direct contact between the type diffusion layer and the n-type polycrystalline silicon. Thus, the n-type polycrystalline silicon can be embedded in the contact hole in one step regardless of the type of the diffusion layer. Further, the contact resistance is low because the n-type polycrystalline silicon can be used instead of the p-type polycrystalline silicon which has a high resistance for forming the clusters and diffusing phosphorus in the insulating film into the contact. Become.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments thereof. FIG. 3 is a schematic cross-sectional view showing a step of filling a contact hole according to the present invention. Figure 3 (a)
As shown in FIG. 3, a p-type diffusion layer 2 (BF ₂ ⁺ 25ke
V, 3 × 10 ¹⁵ cm ^-2 ), n-type diffusion layer 3 (As 40keV, 5 × 10
¹⁵ cm ^-2 ) and the element isolation region 4 are formed. An insulating film SiO _2, 5, 5 is deposited on the surface, and contact holes 6, 7 having a diameter of 0.6 μm, a depth of 1.7 μm and an aspect ratio of 2.8 are respectively formed on the p-type diffusion layer 2 and the n-type diffusion layer 3. Form.

Next, as shown in FIG. 3 (b), a Ti film 8 is deposited to a thickness of 100 nm by a sputtering method, and Si ₂ H ₆ gas and PH ₃ gas are reacted at 500 ° C. thereon by using a low pressure vapor phase growth apparatus. While depositing 400 nm of n-type amorphous silicon 13,
Fill the contact holes 6 and 7. As shown in FIG. 3 (c), the n-type amorphous silicon 13 and the Ti film 8 deposited above the insulating film SiO ₂ 5 are removed by etching back by the reactive ion etching method, and the contact holes 6, 7 are formed. An n-type amorphous silicon plug is formed inside. Annealing is performed at 900 ° C. for 10 seconds to activate the dopant and to change the n-type amorphous silicon plugs 13 and 13 into n-type polycrystalline silicon plugs.
Change to 71,71.

Then, as shown in FIG. 3 (d), an AlSi film is deposited to a thickness of 800 nm by a sputtering method, and etching and sintering at 450 ° C. for 30 minutes are performed to form an AlSi wiring 14. The diameter is 0.6 μm and the depth is 1.7.
The contact resistance of μm, aspect ratio 2.8 is about 90 to 100 Ω for n-type contact and about 120 to 13 for p-type contact.
The low value of 0 Ω forms a good buried contact in polycrystalline silicon.

After the Ti film 8 shown in FIG. 3 (b) is deposited to 100 nm, TiN is deposited using a sputtering device to bond the n-type polycrystalline silicon plug 71 to the p-type diffusion layer 2. The prevention can be further strengthened.

[0015]

As described above, in the method of manufacturing a semiconductor device of the present invention, it is possible to suppress an increase in contact resistance even if the aspect ratio of the contact hole increases. Further, since it is not necessary to separate the doping depending on the type of the underlying diffusion layer, the present invention has excellent effects such as shortening the processing step.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a step of filling a contact hole with polycrystalline silicon.

FIG. 2 is a schematic cross-sectional view showing a step of filling a contact hole with polycrystalline silicon.

FIG. 3 is a schematic cross-sectional view showing a step of filling a contact hole according to the present invention.

[Explanation of symbols]

 1 Si substrate 2 p-type diffusion layer 3 n-type diffusion layer 4 element isolation region 5 insulating film 6 p-type contact hole 7 n-type contact hole 8 Ti film 9 metal wiring 10 polysilicon film 12 polycrystalline silicon 13 n-type amorphous Silicon 14 AlSi wiring 61 p-type silicon plug 71 n-type silicon plug

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which polycrystalline silicon is embedded in a contact hole connected to a diffusion layer to form a contact, a metal thin film is deposited on the contact hole, and n-type polycrystalline silicon is embedded in the surface thereof. 1. A method for manufacturing a semiconductor device, comprising forming a contact by using.