JPH06310458A - Semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To form a stable low-resistance contact regardless of the types of a base diffused layer without increasing the number of processes by metallizing a polycrystalline silicon plug which fills a contact hole so as to flatten it by permitting the plug to contain phosphorus and aluminum. CONSTITUTION:On an n-type silicon substrate 1, the p+ source/drain area 41, a p-well 42 and an n+ source/drain area 43 are previously formed, and a contact hole 3 is formed on an SiO2 film 2 which includes gate electrode 7 composed of polycrystalline silicon. Then, SiH4 is permitted to flow, a phosphorus doped polycrystalline silicon film 80 is formed by lowpressure CVD and the surface is flattened. The film 80 is etched back so as to leave the polycrystalline silicon plug 8 only in the contact hole 3 and the whole surface is flattened. Then, Al wiring 5 is formed by Al deposition and a photo process. The series of processes is completed by annealing the Al in a N2 atmosphere for 30 minutes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element in which a wiring made of aluminum is connected to a predetermined region of a semiconductor substrate or to a lower wiring in a contact hole formed in an insulating film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, wiring connection in a semiconductor device has been
As shown in FIG. 2, a contact hole (contact hole) 3 is opened in the SiO ₂ film 2 as a surface protective film on the p-type silicon substrate 11, and the Al wiring 5 is contacted with the n ⁺ diffusion layer 4 in the contact hole. By doing so, the n ⁺ region 4 and the wiring 5 have been connected. Similarly, as shown in FIG. 3, the upper layer wiring 52 and the lower layer wiring 51 are connected through the contact hole 3 formed in the interlayer insulating film 6. In recent years, the miniaturization of semiconductor devices has been remarkably advanced, and along with this, the diameter of contact holes has become smaller and smaller and the shape has also become a high aspect ratio. When the aspect ratio becomes high, a step h is formed on the surface of the wiring 5 as shown in FIGS. 2 and 3, and a step coverage defect of a layer thereabove tends to occur. Further, as shown in FIG. 4, when the aspect ratio b / a becomes high, disconnection of the wiring 5 occurs. For this reason, a technique for filling the contact hole has been required. As the hole filling technology, a method of filling with metal such as selective tungsten or blanket tungsten, or Nagatomo et al. Reported at the 49th Annual Meeting of the Applied Physics Society of Japan (Autumn), 6p-A-13, 14 (1988) p.654. The method of completing the plug by depositing the polycrystal silicon that has been deposited and then etching it back, Sasaki et al. 32nd Annual Meeting of the Applied Physics Society (Spring)
, 3p-P-12 (1985) p.517, there is a method using selective polycrystalline silicon. However, each technology has merits and demerits, and it has not reached a level capable of mass production.

Recently, a low resistance contact technique using a polycrystalline silicon plug has been developed as reported by Hamajima et al. In "Semiconductor World" 1989.12.p103. This technique consists of (1) ion implantation of n and p impurities into a polycrystalline silicon plug deposited in a contact hole according to the type of the underlying diffusion layer, (2) activation of the diffusion layer and the inside of the polycrystalline silicon plug. (3) The type of the ion-implanted impurities is P ⁺ , p for the n-type, and the impurities are activated at the same time by short-time annealing at 1000 ° C. for 10 seconds.
By adopting a method such as B ^{+ for} the shape, a low contact of about 60 Ω for the n-type plug and about 120 Ω for the p-type plug even with a contact hole of 0.8 μm thickness and 0.6 μm diameter There is a report that resistance was obtained.

[0004]

However, in the low resistance contact technique using the above-mentioned polycrystalline silicon plug, the n and p impurities are separately ion-implanted depending on the type of the underlying diffusion layer. It is unavoidable that the number increases. An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a semiconductor element and a manufacturing method thereof for forming a low resistance contact of a polycrystalline silicon plug in a contact hole having a high aspect ratio without increasing the number of steps. .

[0005]

In order to achieve the above object, the semiconductor element of the present invention has contact holes formed in an insulating film filled with polycrystalline silicon containing phosphorus and aluminum. . The contact hole may be formed in the insulating film on the semiconductor substrate or in the insulating film on the lower wiring. In such a semiconductor element manufacturing method, after the contact holes are filled with polycrystalline silicon containing phosphorus, Al wiring is brought into contact with the polycrystalline silicon filling the contact holes and further annealed.

[0006]

[Function] Since polycrystalline silicon with which the contact holes are filled, that is, polycrystalline silicon contains phosphorus and Al,
It electrically functions as a metal plug and can be used as a low resistance contact regardless of the type of the underlying diffusion layer. Moreover,
Such a polycrystalline silicon plug can be easily obtained by preliminarily doping phosphorus into polycrystalline silicon and diffusing Al of the wiring in contact therewith by annealing.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A polycrystalline silicon plug forming process of an embodiment in a CMOS of the present invention will be described below with reference to FIGS. 1 (a) to 1 (d) in which parts common to those in FIG. The n-type silicon substrate 1 has a P-channel MOSFET.
P ⁺ source / drain region 41, N-channel MOSFE
The p well 42 of T and the n ⁺ source / drain region 43 of the surface layer thereof are already formed, and the SiO _{2 having} a thickness of 0.8 μm including the gate electrode 7 made of polycrystalline silicon thereon is formed.
A contact hole 3 having a diameter of 0.6 μm is formed in the film 2 [FIG. 1 (a)]. Next, SiH ₄ is 1.5 l / mm and PH ₃ is 0.25 l
/ Min flow rate, vacuum degree 2.5 mbar, deposition temperature 600 ℃
Then, a phosphorus-doped polycrystalline silicon film 80 having a phosphorus concentration of 7 mol% is formed to a thickness of 1 .mu.m by a deposition time of 2.5 H by the low pressure CVD method in FIG. 1 and the surface is made flat [FIG. After that, the entire surface is flattened by etching back until the polycrystalline silicon plug 8 remains only in the contact hole 3 portion [FIG. 1 (c)]. Next, the Al wiring 5 is formed through a normal 1 .mu.m thick Al vapor deposition (1 .mu.m thick) and a photo process [FIG. 1 (d)]. After that, a series of processes is completed by annealing Al at 450 ° C. for 30 minutes in an N ₂ atmosphere. Since the Al is diffused into the polycrystalline silicon by the annealing of Al, the film thickness of the Al wiring 5 on the polysilicon plug 8 is finally reduced to 0.5 μm. At this time, the contact resistance of the plug 8 was about 100 Ω in both N channel and P channel, and a low resistance contact was obtained.

By forming a polycrystalline silicon plug that fills the contact hole formed in the interlayer insulating film by a similar method, it was possible to achieve a low resistance contact for the connection between the lower layer Al wiring and the upper layer Al wiring.

[0009]

According to the present invention, a polycrystalline silicon plug which fills a contact hole and is flattened is metallized by containing phosphorus and Al, so that a stable low resistance contact can be obtained regardless of the type of the underlying diffusion layer. It can be formed, and there is no need to increase extra steps by utilizing the annealing of Al wiring. This makes it possible to cope with the miniaturization of semiconductor elements.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the steps of forming a polycrystalline silicon plug according to an embodiment of the present invention in the order of (a) to (d).

FIG. 2 is a sectional view of a connection portion of a conventional single-layer wiring.

FIG. 3 is a sectional view of a connection portion of a conventional two-layer wiring.

FIG. 4 is a cross-sectional view of a defect generated in a high aspect ratio contact hole.

[Explanation of symbols]

1 n-type silicon substrate 2 SiO ₂ film 3 contact hole 41, 43 source / drain region 42 p well 5 Al wiring 7 gate electrode 8 polycrystalline silicon plug 80 polycrystalline silicon film

Claims (4)

[Claims] 1. A semiconductor device characterized in that a contact hole formed in an insulating film is filled with polycrystalline silicon containing phosphorus and aluminum. 2. The semiconductor device according to claim 1, wherein the contact hole is formed in the insulating film on the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the contact hole is formed in the insulating film on the lower wiring. 4. A contact hole is filled with polycrystalline silicon having phosphorus added thereto, and then aluminum wiring is brought into contact with the polycrystalline silicon filling the contact hole, followed by annealing. A method of manufacturing a semiconductor device according to any one of the above.