KR920015645A - LDD의 사리사이드(Salicide) 공정방법 - Google Patents
LDD의 사리사이드(Salicide) 공정방법 Download PDFInfo
- Publication number
- KR920015645A KR920015645A KR1019910000197A KR910000197A KR920015645A KR 920015645 A KR920015645 A KR 920015645A KR 1019910000197 A KR1019910000197 A KR 1019910000197A KR 910000197 A KR910000197 A KR 910000197A KR 920015645 A KR920015645 A KR 920015645A
- Authority
- KR
- South Korea
- Prior art keywords
- ldd
- salicide process
- forming
- titanium
- sariside
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 2
- 229910052719 titanium Inorganic materials 0.000 claims 2
- 239000010936 titanium Substances 0.000 claims 2
- 238000001816 cooling Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 LDD 공정도.
Claims (1)
- 질화물 측벽을 형성한 후 먼저 n+·p+S/D를 형성하여 고온에서 S/D 가열 냉각처리하는 단계와, 티타늄을 증착시켜 사리사이드(50)로 처리한후 선택에칭에 의해 티타늄을 제거하여 사리사이드(50)를 형성하는 단계와, n-,p-I/I을 한 후 저온에서 가열냉각하여 n-·p-S/D를 형성하여 LDD구조를 완성시키는 단계를 포함하여 구성된 것을 특징으로 하는 LDD의 사리사이드 공정방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000197A KR940002775B1 (ko) | 1991-01-09 | 1991-01-09 | 반도체 소자의 제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000197A KR940002775B1 (ko) | 1991-01-09 | 1991-01-09 | 반도체 소자의 제조방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015645A true KR920015645A (ko) | 1992-08-27 |
| KR940002775B1 KR940002775B1 (ko) | 1994-04-02 |
Family
ID=19309556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000197A KR940002775B1 (ko) | 1991-01-09 | 1991-01-09 | 반도체 소자의 제조방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940002775B1 (ko) |
-
1991
- 1991-01-09 KR KR1019910000197A patent/KR940002775B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940002775B1 (ko) | 1994-04-02 |
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| Date | Code | Title | Description |
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| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050318 Year of fee payment: 12 |
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| LAPS | Lapse due to unpaid annual fee |