KR920013094A - Even Parity Calculator - Google Patents

Even Parity Calculator Download PDF

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Publication number
KR920013094A
KR920013094A KR1019900022786A KR900022786A KR920013094A KR 920013094 A KR920013094 A KR 920013094A KR 1019900022786 A KR1019900022786 A KR 1019900022786A KR 900022786 A KR900022786 A KR 900022786A KR 920013094 A KR920013094 A KR 920013094A
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KR
South Korea
Prior art keywords
latch
even parity
logical
simultaneous
bp8resx
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Application number
KR1019900022786A
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Korean (ko)
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KR930002851B1 (en
Inventor
엄두섭
김홍주
김재근
Original Assignee
경상현
재단법인 한국전자통신연구소
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Publication of KR920013094A publication Critical patent/KR920013094A/en
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Publication of KR930002851B1 publication Critical patent/KR930002851B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음No content

Description

이븐 패리티 계산기Even Parity Calculator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

재1도는 본 발명에 의한 전체 구성 블럭도, 제2도는 계산 회로도, 제3도는 저장 회로도.1 is an overall block diagram of the present invention, FIG. 2 is a calculation circuit diagram, and FIG. 3 is a storage circuit diagram.

Claims (3)

동기식 디지틀 다중장치의 기본 계위인 STM-1(Synchrenous Transport Module-1)에서, BIP(Bit Interleaued Parity)값을 처리하는 장치에 있어서, 프레임 데이터와 동시래치 신호(bp8resx)를 입력하여 이븐 패리티로 BIP를 계산하여 출력하는 이븐 패리티 처리수단(11); 상기 이븐 패리티 수단(11)에 연결되어 상기 이븐 패리티 수단(11)의 출력값이 BIP계산값을 19.44M클럭펄스에 동기시켜 출력하는 제1래치 수단(12); 상기 제1래치수단(12)에 연결되어, 상기 동시래치 신호(bp8resx), 19.44M 클럭펄스, 파워 리셋트 신호와 상기 제1래치수단(12)의 출력 값인 BIP계산값을 입력하여 한 프레임에 대한 BIP계산값만을 출력하도록 하는 제2래치수단(21)으로 구성된 것을 특징으로 하는 이븐 피리티 계산기.In the device that processes the Bit Interleaued Parity (BIP) value in the Synchrenous Transport Module-1 (STM-1), which is the basic level of the synchronous digital multiple device, inputs the frame data and the simultaneous latch signal (bp8resx) to the BIP with even parity. Even parity processing means 11 for calculating and outputting the; A first latch means (12) connected to the even parity means (11) and outputting the output value of the even parity means (11) in synchronization with a 19.44 M clock pulse; It is connected to the first latch means 12, and inputs the simultaneous latch signal (bp8resx), 19.44M clock pulse, power reset signal and the BIP calculation value which is the output value of the first latch means 12 in one frame. An even pyritic calculator, characterized in that the second latch means for outputting only the BIP calculation value for the (21). 제1항에 있어서, 상기 이븐 패리티 처리수단(11)은, 상기 동시래치신호(bp8resx)를 입력하여 인버팅The inverse parity processing unit (11) according to claim 1, wherein the even parity processing unit (11) inputs the simultaneous latch signal (bp8 resx) to invert. (Inverting)하는 부정논리 수단(U1);상기 동시래치신호(bp8resx)와 프레임 데이터를 논리곱 처리하는 제1논리곱수단(U3); 상기 동시래치신호(bp8resx)와 프레임 데이터를 논리합 처리하는 제1논리합 수단(U5); 상기 부정논리수단(U1)에 하나의 입력이 연결되고 다른 입력은 제1래치수단(12)에 연결된 제2논리곱 수단(U2); 상기 제2논리곱 수단(U2)과 제1논리곱 수단(U3) 각각의 출력단에 두입력단이 연결된 제2논리합 수단(U5)으로 구성된 것을 특징으로 하는 이븐 패리티 계산기.Negative logic means (U1) for inverting; a first logical means (U3) for performing an AND operation on the simultaneous latch signal (bp8resx) and frame data; First logical sum means (U5) for ORing the simultaneous latch signal (bp8resx) and frame data; A second logical multiplier (U2) connected to the negative logic unit (U1) and one input connected to the first latch unit (12); An even parity calculator, characterized in that it comprises a second logical sum means (U5) having two input ends connected to an output end of each of the second logical means (U2) and the first logical means (U3). 제1항에 있어서, 상기 제1래치수단(12)과 제2래치수단(21)은 D플립플톱으로 구성함을 특징으로 하는 이븐 패리티 계산기.The even parity calculator according to claim 1, wherein the first latch means (12) and the second latch means (21) comprise a D flip-top. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022786A 1990-12-31 1990-12-31 Even parrity calculator KR930002851B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022786A KR930002851B1 (en) 1990-12-31 1990-12-31 Even parrity calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022786A KR930002851B1 (en) 1990-12-31 1990-12-31 Even parrity calculator

Publications (2)

Publication Number Publication Date
KR920013094A true KR920013094A (en) 1992-07-28
KR930002851B1 KR930002851B1 (en) 1993-04-12

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Application Number Title Priority Date Filing Date
KR1019900022786A KR930002851B1 (en) 1990-12-31 1990-12-31 Even parrity calculator

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KR930002851B1 (en) 1993-04-12

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