KR920010781B1 - Process for plating a printed circuit board - Google Patents
Process for plating a printed circuit board Download PDFInfo
- Publication number
- KR920010781B1 KR920010781B1 KR1019900020181A KR900020181A KR920010781B1 KR 920010781 B1 KR920010781 B1 KR 920010781B1 KR 1019900020181 A KR1019900020181 A KR 1019900020181A KR 900020181 A KR900020181 A KR 900020181A KR 920010781 B1 KR920010781 B1 KR 920010781B1
- Authority
- KR
- South Korea
- Prior art keywords
- plating
- connector
- pcb
- layer
- copper
- Prior art date
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Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
제1도는 종래의 평면도,1 is a conventional plan view,
제2도는 제1도의 정면도.2 is a front view of FIG.
제3도는 본 발명의 평면도.3 is a plan view of the present invention.
제4도는 본 발명의 도금선을 빼내는 방법을 도시한 예시도,4 is an exemplary view showing a method of removing the plating wire of the present invention;
제5도는 종래의 사시단면도,5 is a conventional perspective cross-sectional view,
제6도는 본 발명의 사시단면도.6 is a perspective cross-sectional view of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : P.C.B 2 : 도금부위1: P.C.B 2: Plating part
3 : 구리부 4 : 관통공3: copper part 4: through-hole
5 : 커넥터 6 : 단자5 connector 6 terminal
7 : 구리층 8 : 도금선7: copper layer 8: plating wire
10 : 도금전극10: plating electrode
본 발명은 인쇄회로기판(Printed Circuit Board 이하, PCB라 칭함.)에 적용되는 도금(Gold Plate) 공법에 관한 것으로써, 특히, PCB의 도금 부위인 상부면과 하부면 사이 중앙부위에 구리층을 형성시켜서 도금시 금손실을 최소화 함은 물론, 완제품 가공을 위한 PCB절단시 발생될 수 있는 커넥터간의 단락(short)을 방지할 수 있는 PCB의 도금공법에 관한 것이다.The present invention relates to a plating method applied to a printed circuit board (hereinafter, referred to as a PCB). In particular, a copper layer is formed on a central portion between an upper surface and a lower surface of a PCB. It is related to the plating method of the PCB to minimize the gold loss during the plating to form, as well as to prevent a short (short) between the connectors that can be generated when cutting the PCB for processing the finished product.
종래의 PCB제조기술에 있어서의 커넥터 부분에 대한 도금은, 제1도 내지 제2도 및 제5도에 도시한 바와 같이, PCB(1) 외층의 도금선(8)을 이용하여 도금와이어를 연결하는 방법을 사용하였다. 그러나, 이 방법은 PCB(1) 완제품을 제작하는 과정중 하나인 절단(Rounting)작업시 도금부위(2, 커넥터 단자)의 구리부(3)가 들뜨거나 돌기(Burr)가 발생되므로 커넥터(5) 소켓의 접촉이 불완전할 뿐만 아니라, PCB외층을 이용하여 도금선을 인출하게 되므로 꼭 필요한 부위에만 도금하는 것이 아니라 도금이 필요없는 리이드 부분까지도 도금이 행해질 수 있으므로 금손실이 많아진다는 문제점이 있었다.Plating of the connector portion in the conventional PCB manufacturing technique, as shown in Figs. 1 to 2 and 5, the plating wire is connected using the plating wire 8 of the outer layer of the PCB (1) Method was used. However, in this method, the copper part 3 of the plating part 2 and the connector terminal is lifted or a burr is generated during the cutting process, which is one of the processes of manufacturing the finished product of the PCB 1. ) As the contact of the socket is incomplete, and the plating line is drawn out using the PCB outer layer, plating may be performed on the lead portion that does not require plating, but plating may be performed only on the necessary portion, thereby increasing the gold loss.
따라서, 본 발명은 이와 같은 종래의 문제점을 감안하여 이루어진 것으로써, 도금을 행하기 위하여 외층으로 뽑아내는 커넥터가 필요없게 하여 커넥터 엣지(edge)부분이 깨긋해져서 돌기가 발생하지 않음으로써 접촉불량을 방지할 수 있는 PCB의 도금공법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made in view of such a conventional problem, and it is unnecessary to remove the connector to the outer layer in order to perform plating so that the edge of the connector is broken so that no projection occurs, thereby preventing contact failure. The purpose is to provide a plating method for PCB.
본 발명의 다른 목적은, 도금시 금손실을 최소화하고, 완제품 가공을 위한 PCB 절단시 커넥터간에 발생할 수 있는 단락을 최대한 방지할 수 있는 PCB의 도금공법을 제공하는데 있다.Another object of the present invention is to provide a PCB plating method that can minimize gold loss during plating and prevent a short circuit that may occur between connectors when cutting a PCB for processing a finished product.
이와 같은 목적을 달성하기 위한 본 발명은, PCB의 상부면과 하부면에 서로 대향되도록 형성된 커넥터의 구리부에 도금부위를 형성시키는 도금공법에 있어서, 상기 커넥터의 구리부에 최적상태의 도금이 행해지도록 도금부위의 상부면과 하부면사이 중앙부위에 구리층을 형성시키고, 상기 커넥터는 외층으로 노출되지 않고 내층으로 나오도록하며, 상기 커넥터에 소정직경으로 형성된 관통홀과 연결되는 도금선은 PCB내층을 통해서 외부로 인출하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a plating method for forming a plating portion on a copper portion of a connector which is formed to face each other on an upper surface and a lower surface of a PCB. A copper layer is formed at a central portion between the upper and lower surfaces of the plating portion, and the connector is not exposed to the outer layer and comes out to the inner layer, and the plating line connected to the through hole formed in the connector at a predetermined diameter is the inner layer of the PCB. It is characterized in that withdrawn to the outside through.
이하, 본 발명의 실시예를 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
제3도는 본 발명의 평면도, 제4도는 본 발명의 도금선을 빼내는 방법을 도시한 예시도, 제6도는 본 발명의 사시도이다.FIG. 3 is a plan view of the present invention, FIG. 4 is an exemplary view showing a method of removing the plating wire of the present invention, and FIG. 6 is a perspective view of the present invention.
제3도 내지 제4도 및 제6도에 있어서, (1)은 전자회로가 구성되는 PCB, (5)는 커넥터로써, 상기 PCB(1)의 상부면과 하부면에 서로 대향되도록 일정간격을 두고 형성하며, 그 하부에 형성된 소정 두께를 구리부(3)와, 이 구리부(3)의 상부면에 얇은 두께로 형성된 도금부위(2)로 구성된다. (7)은 상기 PCB(1)의 상부면과 하부면에 서로 대향되도록 형성된 구리부(3)의 도금부위(2)의 중앙부위에 형성시킨 구리층으로써, PCB(1)의 내층을 통해 외부로 인출되도록 PCB(1)의 내층에 내설되는 내층도금인출선(8a)상에 형성된다.In Figures 3 to 4 and 6, (1) is a PCB is composed of an electronic circuit, (5) is a connector, a predetermined interval so as to face each other on the upper and lower surfaces of the PCB (1). And a predetermined thickness formed under the copper portion 3, and a plating portion 2 formed on the upper surface of the copper portion 3 in a thin thickness. (7) is a copper layer formed on the central portion of the plating portion (2) of the copper portion (3) formed to face each other on the upper surface and the lower surface of the PCB (1), the outside through the inner layer of the PCB (1) It is formed on the inner layer plating lead line 8a which is built in the inner layer of the PCB 1 so as to be drawn out.
한편, 상기 내층도금인출(8a)을 통해 도금선(8)이 PCB(1)의 외부로 인출되며, 이 도금선(8)은 도금전극(10)에 배설된다. 한편, 상기 커넥터(5)의 소정부위에는 소정직경을 갖는 관통홀(4)이 형성되며, 이 관통홀(4)이 도금선(8)과 연결되어서 도금이 행해지도록 되어 있다.Meanwhile, the plating line 8 is drawn out of the PCB 1 through the inner layer plating lead 8a, and the plating line 8 is disposed on the plating electrode 10. On the other hand, a through hole 4 having a predetermined diameter is formed in a predetermined portion of the connector 5, and the through hole 4 is connected to the plating line 8 so that plating is performed.
이와 같은 구성을 갖는 본 발명에 있어서의 도금공법은 전기분해를 이용해서 커넥터(5)의 외부에 노출되는 부위에 대해서만 도금을 행하며 도금시 두께는 50㎛까지 가능토록 한다.In the plating method of the present invention having such a configuration, plating is performed only on a portion exposed to the outside of the connector 5 using electrolysis, and the plating thickness can be up to 50 µm.
커넥터(5)의 구리부(3)에 대한 도금부위(2)형성은, PCB(1) 내층을 이용해서 외부로 인출한 도금선(8)을 통해 관통공(4)으로 전류가 흐르도록 함으로써 이루어진다. 이때, 도금부위(2)는 커넥터(5) 외층부위 일정 부분에만 형성되며, 리이드 따위는 행해지지 않는다.Formation of the plating portion 2 on the copper portion 3 of the connector 5 is such that current flows through the through hole 4 through the plating wire 8 drawn outward using the inner layer of the PCB 1. Is done. At this time, the plating part 2 is formed only in a predetermined part of the outer layer part of the connector 5, and no lead is performed.
이와 같이 본 발명의 PCB의 도금공법에 의하면, 커넥터(5)가 외층으로 노출되지 않고 내층으로 나오기 때문에 도금시 금손실이 최대한 방지되며, 종래와 같이 도금을 행하기 위해 인출하는 단자가 필요없게 되므로 커넥터(5)의 엣지부분이 편탄해져서 접촉불량도 방지할 수 있다.As described above, according to the PCB plating method of the present invention, since the connector 5 is not exposed to the outer layer and comes out to the inner layer, gold loss is prevented as much as possible during plating, and thus the terminal to be drawn out for plating is not required as in the prior art. The edge portion of the connector 5 is flattened to prevent contact failure.
뿐만 아니라, PCB절단시 커넥터간에 발생될 수 있는 단락을 적극적으로 방지하는등 매우 커다란 효과가 있는 것이다.In addition, there is a very large effect, such as actively prevent a short circuit that may occur between the connector when cutting the PCB.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900020181A KR920010781B1 (en) | 1990-12-08 | 1990-12-08 | Process for plating a printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900020181A KR920010781B1 (en) | 1990-12-08 | 1990-12-08 | Process for plating a printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920012531A KR920012531A (en) | 1992-07-27 |
| KR920010781B1 true KR920010781B1 (en) | 1992-12-17 |
Family
ID=19307243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900020181A KR920010781B1 (en) | 1990-12-08 | 1990-12-08 | Process for plating a printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR920010781B1 (en) |
-
1990
- 1990-12-08 KR KR1019900020181A patent/KR920010781B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920012531A (en) | 1992-07-27 |
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