KR920008219B1 - Vertical pulse generating circuit - Google Patents

Abstract

The phase of the vertical lock pulse is adjusted by an external adjusting circuit to provide exact vertical synchronism according to special reproduction modes. The generator comprises an edge detection circuit (10) for generating trigger pulse by detecting rising edge or falling edge of video head switch signal (HS), a counter (20) reset by the rising edge trigger pulse generated by the edge detection circuit to start counting, and a mono-stable multivibrator (30) operated by the falling edge trigger pulse generated by the edge detecting circuit (10) to trigger the counter (20) for adjusting time.

Description

Phase Adjustable Vertical Fixed Pulse Generator Circuit

1 is a block diagram of a vertical fixed pulse generating circuit according to the present invention.

2 is a detailed circuit diagram of FIG.

3 is a detailed circuit diagram of a multivibrator included in the detailed circuit diagram of FIG.

4 is a waveform diagram of each part of the circuit diagram of FIG.

5 is a state diagram of a vertical fixed pulse generated in accordance with a video head switching signal during operation of the circuit according to the present invention.

The present invention relates to a vertical fixed pulse generating circuit used in a video tape recorder system, and more particularly, to a phase-variable vertical fixed pulse generating circuit capable of supplying a stable vertical synchronizing signal in a search mode or a stop mode.

When the video tape recorder synchronizes the system, the recording mode is used to synchronize the system using the vertical synchronization signal of the video signal. In the playback mode, the system synchronization is performed by the vertical synchronization signal of the signal recorded on the tape.

However, because the search mode or the stop mode when there is not available the vertical synchronization signal of 60H _Z by dividing the local system clock in the servo control integrated device must generate a vertical fixed-pulse (Vertical Pulse Lock), as a separate vertical synchronizing signal.

The conventional technique related to the technique of generating the vertical fixed pulse causes the vertical fixed pulse to be generated after a predetermined time delay at the rising edge and the falling edge of the video head switching signal.

That is, according to the signal triggered by the rising edge and the falling edge in the video head switching signal, the vertical fixed pulse is generated constantly after a fixed time.

For this reason, the video signal displayed on the screen and the vertical synchronization signal do not coincide depending on the position of the video head attached to the drum motor.

In addition, since the video head switching time and the time until the vertical fixed pulse are generated in the various search and stop modes are different from each other, the video signal cannot be faithfully reproduced when displayed on the CRT screen so that a blanking portion appears on the screen.

In other words, the video signal read from the video head and the vertical fixed pulse are not synchronized so that the screen is shifted downward or upward, or in extreme cases, the bottom and top of the screen array are reversed.

In addition, the conventional technology has a problem in that there is no method for synchronizing when the screen is not synchronized because the phase between the video head switching signal and the vertical fixed pulse signal is always fixed.

An object of the present invention is to provide a phase-variable vertical fixed pulse generating circuit capable of generating stable images by generating vertical fixed pulses suitable for each mode in a stop mode or an installation mode.

Another object of the present invention is to provide a phase-variable vertical fixed pulse generator capable of varying the phase between the video head switching signal and the vertical fixed pulse having a monostable multivibrator that can adjust the time constant from the outside.

In order to achieve the above object, the present invention provides an edge detection and control unit for detecting a rising edge or a falling edge of a video head switching signal and outputting a trigger pulse corresponding to the detection signal, and a rising edge in the edge detection and adjustment unit. The counter circuit resets by a trigger pulse output at the time of detection and starts the counter, and is operated by the trigger pulse output at the detection of the falling edge by the edge detection and control unit to control the time by triggering the counter circuit. It is characterized by consisting of a vibrator.

The monostable multivibrator provides a phase-variable vertical fixed pulse generating circuit which can vary a time constant by externally configuring a capacitor and a load resistor connected to a pad.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of a pulse generating circuit according to the present invention in detail.

1 is a block diagram of a vertical fixed pulse generating circuit according to the present invention. As shown in the block diagram, the pulse generation circuit according to the present invention detects the rising edge or falling edge of the video head switching signal HS, and detects and outputs a trigger pulse corresponding to the detection signal 10. And a counter circuit 20 which is reset by a trigger pulse output when the rising edge is detected by the edge detection and adjustment unit 10 to start a counter, and the edge detection and adjustment unit 10 detects a falling edge. It is composed of a monostable multivibrator 30 which is operated by a trigger pulse output at the time and controls the time by triggering the counter circuit 20 after a predetermined time delay.

In this configuration, the phase change is performed so that the phase between the rising edge and the vertical fixed pulse of the video head switching signal is fixed at the rising edge of the video head switching signal, and the phase is changed by a monostable multivibrator at the falling edge of the video head switching signal. Means are provided.

The configuration is more clearly explained in FIG. 2, which is a detailed circuit diagram of the block diagram of FIG.

The circuit for controlling the counter in the edge detection and control unit 10 includes a flip-flop F1 for detecting a falling edge of the inverted pulse signal DEG3 of the video head switching signal and a rising of the pulse signal DFE3. Is connected to the flip-flop F2 detecting the edge, the plurality of gates G11 (G15) and G16 connected to the flip-flop F2 and the flip-flop F4 for signal transmission. And a gate G14 connected to the outputs of the gates G12 and G13 and supplying a reset signal to the counter circuit 20.

In the drawing, the gates G7 and G9 and the inverting inverters I2 and I3 connected to the flip-flop F1 are for signal transmission.

The clock conversion circuit 5 configured in the edge detection and adjustment unit 10 is connected to the gates G4 and G5 and the gates G4 and G5, each of which includes latches for supplying clocks CC1 and CC2. And a signal transfer gate G3 (G20 (G21)), a flip-flop F5 connected to the gate G1 to send a signal oscillation trigger signal, and a signal transfer flip-flop F6 and F3. Here, the pulse supplied to the node n7 becomes a counter pulse.

The counter circuit 20 constitutes a counter by sequentially connecting the flip-flops CF1-CF10 for the counter, and the gates G21 to G24 are connected to the output side thereof, and the gate G26 for outputting the signal of the decimal number 739. ) And a gate G25 for outputting a signal of the decimal number 171.

In this case, the counter flip-flops CF1-CF10 are 2 ⁰ , 2 ¹ , 2 ² ,. Generates count output up to 2 ⁹ .

The monostable multivibrator 30 is composed of gates G30-G33 each of which constitutes a latch circuit, a gate G34 for receiving the output thereof, and a drive gate I4-I6 for reverse driving. The output of the gates is supplied to a monostable multivibrator MT.

Reference numeral DFG3 denotes a signal in which the video head switching signal is inverted, reference numeral SD13 denotes a signal outputting an H level signal only in the stop mode and various search modes (special mode), and an L level signal in the remaining modes. VLK is a vertical fixed pulse signal output stage which is the actual output of the circuit of this invention.

Reference numeral CC1 denotes a clock signal of 3.58MH _Z / 2, and reference numeral CC2 denotes a clock signal of 3.58MH _Z / 4. Reference numeral MPMM denotes an input pulse of the monostable multivibrator MT, and reference numeral VPOUT denotes an output signal of the monostable multivibrator MT.

FIG. 3 is a specific circuit diagram of the monostable multivibrator MT constituting FIG. 2 and shows that it is implemented by a CMOS circuit.

The circuit includes a switching unit 6 connected to the pad PAD and composed of an NMOS transistor M1, a load resistor RL and a capacitor CI connected to the pad PAD and outputting a comparative voltage charged and charged. And a PMOS transistor M2 to M5, NMOS transistors M6 and M7, which are connected to a comparator 7 for comparing the reference voltage with the charging voltage of the capacitor C1, and a rear end of the comparator 7. And a buffer 8 composed of P. NMOS transistors M8 and M9.

In the present invention configured as described above, the pulse signal DFG3 is a signal in which the video head switching signal is inverted and will be described based on the fourth degree pulse signal DFG3.

At the falling edge of the pulse signal DFG3, the output node n1 of the flip-flop F1 is in the logic L level and the output node n2 of the NAND gate G11 is in the H level. Therefore, the output node n3 of the latch composed of the noar gates G12 and G13 is in the H level state, and the output node n4 of the noa gate G14 which inputs this signal is kept in the L level state. .

Therefore, since the L level signal is applied to the reset terminal R of the flip-flops CF-CF10 in the counter circuit 20, the reset of the downloader circuit 20 is canceled and a counter starts.

At this time, the output node W6 of the noar gate G5 maintains the L level state, and the clock CC2 is cut off, and the clock CC1 is applied to the counter circuit 20 through the nod n7 to count. Will be Since the node n3 is in the H level state, the L-level state signal of the node n5 through the NOA gate G1 is inverted in the inverter I1 so that the T-type flip-flop F1, ( Since it is applied to the reset terminal R of F2, it is reset and the output node n1 of the flip-flop F1 becomes H level again. When the counter circuit 20 counts the counting and becomes 739 as a decimal number, the count outputs of the gates G23, G24, and G26 become H level, and the node n29 outputs a state signal of H level. The output node n15 of the D flip-flop F4 is in the H level state.

Since the status signal of the H level of the output node N15 becomes L level through the noar gate G12, the reset signal of the H level of the node n4 is output by the initial operation as described above, and the counter circuit 20 ) Is reset.

At this time, the node n3 has the gate level G1 as the L level state and the state signal of the L level toggles the flip flop F5 so that the H level state signal of the node n9 passes through the flip flop F6. ) Becomes an L-level signal, so that clock CC1 passes through the no-gate G3, and gates G4 and G5, which constitute a latch circuit, are triggered, and the node n6 is in the H level state. VLK) output becomes H state (rising time).

As a result, after the video head switching signal HS of FIG. 4 becomes H level, 1 / CC × 739 739 = 2 / 3.58MH _Z × 739 = 412.8 Hz = 6.5H. At this time, since the node n6 is at the H level, the counter circuit 20 resets again to perform a counter.

Since the node n6 is in the H level state, the counter clock passes through the clock CC2 and is synchronized with the clock. When the counter circuit 20 counts, the counter clock reaches 171 in decimal. Since the output becomes H level, the node n6 becomes L level and the node n4 becomes H level to reset the count circuit 20. At this time, the horizontal fixed pulse VLK is in the L level state (polling time).

Therefore, the width of the horizontal fixed pulse (VLK) is determined, which is 1 / CC2 × 171 = 3H, the horizontal fixed pulse having a pulse width of 3H is generated by delaying 6.5H at the rising edge of the video head switching signal . Here, 1H = 63.5 Hz.

After that, when the video head switching signal HS becomes L level, the inverted pulse DFG3 becomes H level and the flip-flop F5 of the clock converting circuit 5 is toggled so that the node n16 becomes H level. n17) becomes H level. When the signal becomes the H level signal through the node n16, the monostable multivibrator MT is charged and charged to the inverted voltage level of 2.5V, and the output VPOUT becomes L level and is input to the noar gate G1. do. This signal again toggles the flip-flop F5 of the clock conversion circuit 5.

This output is applied to the flip-flop F6 through the node n9 as described above, and this output passes through the 1/2 clock of the noble gate G3 so that the node n30 is in the H level state for 1/2 clock. Is maintained.

Accordingly, the latch composed of the noah gates G3 and G4 is triggered to bring the node n6 into the H level state. When the node n6 is in the H level state, the clock CC1 is cut off and the clock CC2 is input. When the node n6 becomes H level, the operation is performed as described above, and the node n4 enters the L level state, and the counter circuit 20 counts the clock CC2.

When the node n6 is at the H level, the horizontal fixed pulse signal VLK is at the H level again. When the counter circuit 20 continues to count and 171 is counted in decimal, the node n20 is at the H level. The circuit 20 is reset.

At this time, since the node n6 is at the L level, the horizontal fixed pulse signal VLK has the L level as the falling time. At this time, 1 / CC2 x 171 = 191 kHz = 3H of the horizontal fixed pulse.

As a result, by varying the RC time constant in the monostable multivibrator, it can be changed to a desired value until the time when the horizontal fixed pulse is generated at the falling edge of video head switching.

When the video head switching signal rises again, as described above, a delay of 6.5H occurs, and a horizontal fixed pulse is generated. When the video head switching signal is polled, the monostable multivibrator is triggered and the horizontal fixed pulse is generated again after a predetermined time according to the value of the RC time constant.

In the monostable multivibrator of FIG. 3, when no pulse VPMM is applied to the switching unit 1, the NMOS transistor M1 is maintained in a blocking state, and the capacitor C1 is supplied through the load resistor RL. The power is charged to become a comparative voltage. The voltage is compared by the comparator 7 and output to the output stage buffer 8. When the charge voltage is lower than the reference voltage, the PMOS transistor M2 is turned on and the PMOS transistor M3 is kept turned off. NMOS transistors M6 and M7 are current sources.

In this state, when the switching unit 6 operates and the NMOS transistor M1 is turned on, the MOS transistor of the comparator 7 operates in reverse to the above, and the charging source power is discharged to the capacitor C1.

Therefore, by varying the time constant by varying the external load resistance RL, it is possible to generate an output that adjusts the variable phase according to the desired time.

4 and 5, the present invention provides the flip-flop of FIG. 3 in a repetitive operation in which the video head switching signal HS becomes H level when driving the first head and L level when driving the second head. The edge of the bell is detected by F1) and F2. Flip-flop F1 detects the falling edge, and flip-flop F2 detects the rising edge.

First, the counter circuit 20 is reset by the output of the flip-flop F2 at the rising edge, and the counter count is started until 6.5H by the clock CC2. As in the operation of the counter circuit of FIG. It becomes decimal 739. When the decimal number 739 is counted, it is reset and counted until the 3H period by the clock CC1 by the driving of the clock conversion circuit 5.

This is the same as the operation of the counter circuit of FIG. After the decimal number 171 is counted, the counter circuit 20 is reset and the monostable multivibrator MT is operated to count the counter circuit with a pulse CC2 after the time constant of the capacitor C1 and the load resistor RL. 171 is counted, and this period corresponds to the variable period VR in FIG.

This operation is repeated to generate vertical fixed pulses so that the variable range VR is externally set according to each operation mode in the special playback mode as described above to generate vertical fixed pulses corresponding to the respective operation modes. Can be.

As described above, in order to solve the problem that the vertical synchronization signal recorded on the tape cannot be accurately detected in the special playback mode, the phase of the vertical fixed pulse generated during video head switching can be changed externally. If the synchronization is not correct, a video tape recorder can be provided that can be adjusted externally to provide accurate vertical synchronization for each special playback mode.

Claims (5)

Edge detection and control unit 10 that detects the rising or falling edge of the video head switch signal HS and outputs a trigger pulse corresponding to the detection signal, and the edge detection and detection unit 10 detects the rising edge. The counter circuit 20 is reset by the trigger pulse outputted at the time and is started by the counter pulse 20 which is output by the edge detection and control unit 10 when the falling edge is detected. Phase-variable vertical fixed pulse generating circuit, characterized in that consisting of a monostable multivibrator (30) to adjust the time by triggering. 2. The edge detection and control unit 10 of claim 1, wherein the edge detection and adjustment unit 10 includes a flip-flop F1 for detecting a falling edge of the pulse signal DFG3 in which the video head switching signal HS is inverted, and the pulse signal DFG3. A flip-flop (F2) for detecting the rising edge of the < RTI ID = 0.0 > Fl < / RTI > Gates G12 and G13; Gates G4 and G5 connected to the output of the gate G12 and configured to supply a reset signal to the counter circuit 20 and a latch circuit to supply the clocks CC1 and CC2. A signal transfer gate G3 (G20 to G21) connected to the gates G4 and G5, a flip-flop F5 connected to the gate G1 and sending a trigger pulse for signal transfer, A phase variable vertical fixed pulse generating circuit comprising a flip flop (F3) (F6) for signal transmission connected to a gate element. 2. The counter circuit 20 of claim 1, wherein the counter circuit 20 is connected to an output terminal of the flip-flop CF1-CF10 and the flip-flop CF1-CF10, which are configured to sequentially connect a binary-counted device. A phase variable vertical fixed pulse generation circuit comprising: gate elements (G21-G26) for generating pulses corresponding to an output of 171. The monostable multivibrator (30) according to claim 1, wherein the monostable multivibrator (30) outputs a switching unit (6) connected to a pad (PAD) and composed of an NMOS transistor (M2), and a comparative voltage connected to the pad (PAD). A comparator 7 comprising a load resistor RL and a capacitor C1, a PMOS transistor M2-M5, and an NMOS transistor M6 and M7 to compare the reference voltage with the charging voltage of the capacitor C1. And a buffer (8) connected to the rear end of the comparing unit (7) and composed of PMOS transistors (M8) and (M9). The method of claim 1, wherein the monostable multivibrator 30 is configured to externally configure a capacitor C1 and a load resistor RL connected to the pad PAD to vary the time constant. A phase variable vertical fixed pulse issuing circuit, characterized in that.

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