KR920008103Y1 - 액정 프로젝터의 비데오 신호처리 및 출력회로 - Google Patents
액정 프로젝터의 비데오 신호처리 및 출력회로 Download PDFInfo
- Publication number
- KR920008103Y1 KR920008103Y1 KR2019890018397U KR890018397U KR920008103Y1 KR 920008103 Y1 KR920008103 Y1 KR 920008103Y1 KR 2019890018397 U KR2019890018397 U KR 2019890018397U KR 890018397 U KR890018397 U KR 890018397U KR 920008103 Y1 KR920008103 Y1 KR 920008103Y1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- multiplexer
- rgb
- transistor
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/02—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes by tracing or scanning a light beam on a screen
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims (3)
- 액정을 이용하는 프로젝터에 있어서, 복합 영상신호를 Y/C분리시킨 Y/C분리부(1)의 Y/C신호와 Y/C 분리된 S-VHS신호를 콘트롤 신호로 선택하는 멀티프렉서1(2)와, 상기 멀티플렉서1(2)에서 선택된 Y/C 신호를 R.G.B신호로 복조하는 R.G.B복조부(3)와, 상기 R.G.B복조부(3)에서 복조되어진 R.G.B 신호와 R.G.B 신호로 분리되어 인가되고 R.G.B 처리부(4)에서 일정레벨로 증폭된 R.G.B 신호를 콘트롤 신호로 선택하는 멀티플렉서2(5)와, 상기 멀티플렉서2(5)에서 선택된 신호를 반전시켜 출력시키는 한편 비반전시켜 출력시키는 신호처리부(6)와, 상기 신호처리부(6)에서 반전되어 출력된 신호와 비반전되어 출력된 신호를 콘트롤 신호로 선택하여 액정 모듀울에 교류적으로 인가시키는 멀티플렉서3(7)를 연결 구성시킨 것을 특징으로 하는 액정 프로젝터의 비데오 신호처리 및 출력회로.
- 제1항에 있어서, 신호처리부(6)는 멀티플렉서2(5)에서 선택된 신호를 버퍼링 시키는 트랜지스터(Q1)와, 상기 트랜지스터(Q1)를 통과한 신호를 증폭시키는 트랜지스터(Q2)와, 상기 트랜지스터(Q2)에서 증폭된 신호를 베이스 입력으로 하여 콜렉터와 에미터 측으로 각각 반전된 신호와 비반전된 신호를 출력시키는 트랜지스터(Q3)를 연결 구성시킨 것을 특징으로 하는 액정 프로젝터의 비데오 신호처리 및 출력회로.
- 제1항에 있어서, 멀티플렉서3(7)의 콘트롤 신호는 프레임 주파수가 인가되게 구성하여 멀티플렉서3(7)의 출력이 1프레임 마다 반전되어 출력되게 구성한 것을 특징으로하는 액정 프로젝터의 비데오 신호처리 및 출력회로.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019890018397U KR920008103Y1 (ko) | 1989-12-02 | 1989-12-02 | 액정 프로젝터의 비데오 신호처리 및 출력회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019890018397U KR920008103Y1 (ko) | 1989-12-02 | 1989-12-02 | 액정 프로젝터의 비데오 신호처리 및 출력회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910012543U KR910012543U (ko) | 1991-07-30 |
KR920008103Y1 true KR920008103Y1 (ko) | 1992-11-06 |
Family
ID=19292806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019890018397U Expired KR920008103Y1 (ko) | 1989-12-02 | 1989-12-02 | 액정 프로젝터의 비데오 신호처리 및 출력회로 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR920008103Y1 (ko) |
-
1989
- 1989-12-02 KR KR2019890018397U patent/KR920008103Y1/ko not_active Expired
Also Published As
Publication number | Publication date |
---|---|
KR910012543U (ko) | 1991-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2010688A1 (en) | Fast response picture-in-picture circuitry | |
KR850005206A (ko) | 칼라 비데오 신호 영상 정보처리 및 표시장치 | |
JPS6195629A (ja) | テレビジヨン受像機 | |
US4617563A (en) | Liquid crystal display device | |
JPH02271389A (ja) | フルカラー液晶表示装置 | |
KR920008103Y1 (ko) | 액정 프로젝터의 비데오 신호처리 및 출력회로 | |
US5021886A (en) | Video signal processor for a color liquid crystal display | |
JP5017885B2 (ja) | 液晶表示装置 | |
JP2938264B2 (ja) | 液晶映像表示装置 | |
ATE130720T1 (de) | Fernsehapparat. | |
JPS55153484A (en) | Interlace correction circuit for two screen television receiver | |
JPH05224641A (ja) | 映像表示装置 | |
JPH0537909A (ja) | 液晶映像表示装置 | |
US5258749A (en) | Non-interlace display device | |
JPH05300448A (ja) | 映像表示装置 | |
JP3503303B2 (ja) | 表示装置 | |
JP2611032B2 (ja) | 液晶表示装置 | |
JPH0320104B2 (ko) | ||
KR960015835B1 (ko) | 티브이의 온스크린 영상 표시 회로 및 그 방법 | |
JP2000175116A (ja) | テレビジョン受像機 | |
JPS63142980A (ja) | 液晶表示装置 | |
JPH04271577A (ja) | 液晶表示装置のガンマ補正方式 | |
JPS5943689A (ja) | 表示装置 | |
JPS59144293A (ja) | 小型カラ−テレビジヨン受像機 | |
JPS6167891A (ja) | カラ−デイスプレイ装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19891202 |
|
UA0201 | Request for examination |
Patent event date: 19891202 Patent event code: UA02012R01D Comment text: Request for Examination of Application |
|
UG1501 | Laying open of application | ||
E902 | Notification of reason for refusal | ||
UE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event code: UE09021S01D Patent event date: 19920519 |
|
UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19921007 |
|
E701 | Decision to grant or registration of patent right | ||
UE0701 | Decision of registration |
Patent event date: 19930203 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
|
REGI | Registration of establishment | ||
UR0701 | Registration of establishment |
Patent event date: 19930426 Patent event code: UR07011E01D Comment text: Registration of Establishment |
|
UR1002 | Payment of registration fee |
Start annual number: 1 End annual number: 3 Payment date: 19930421 |
|
UR1001 | Payment of annual fee |
Payment date: 19951030 Start annual number: 4 End annual number: 4 |
|
UR1001 | Payment of annual fee |
Payment date: 19961028 Start annual number: 5 End annual number: 5 |
|
UR1001 | Payment of annual fee |
Payment date: 19961230 Start annual number: 6 End annual number: 6 |
|
UR1001 | Payment of annual fee |
Payment date: 19970826 Start annual number: 7 End annual number: 7 |
|
UR1001 | Payment of annual fee |
Payment date: 19970829 Start annual number: 8 End annual number: 8 |
|
UR1001 | Payment of annual fee |
Payment date: 20001030 Start annual number: 9 End annual number: 9 |
|
UR1001 | Payment of annual fee |
Payment date: 20011030 Start annual number: 10 End annual number: 10 |
|
FPAY | Annual fee payment |
Payment date: 20021031 Year of fee payment: 11 |
|
UR1001 | Payment of annual fee |
Payment date: 20021031 Start annual number: 11 End annual number: 11 |
|
LAPS | Lapse due to unpaid annual fee | ||
UC1903 | Unpaid annual fee |