KR920007356B1 - 트렌치(trench)를 이용한 소자간 격리방법 - Google Patents
트렌치(trench)를 이용한 소자간 격리방법 Download PDFInfo
- Publication number
- KR920007356B1 KR920007356B1 KR1019900003823A KR900003823A KR920007356B1 KR 920007356 B1 KR920007356 B1 KR 920007356B1 KR 1019900003823 A KR1019900003823 A KR 1019900003823A KR 900003823 A KR900003823 A KR 900003823A KR 920007356 B1 KR920007356 B1 KR 920007356B1
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- South Korea
- Prior art keywords
- film
- oxide film
- trench
- etching
- layer
- Prior art date
Links
- 238000002955 isolation Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 claims description 28
- 150000004767 nitrides Chemical class 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009833 condensation Methods 0.000 claims description 2
- 230000005494 condensation Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (3)
- 소자간 격리 공정에 있어서 실리콘층 위의 매몰층(1)에 에피택셜층(2)을 키우고 그 위에 열산화막(3)과 질화막(4) 및 산화막(5)을 각각 500Å, 1000Å, 5000Å의 두께로 증착하는 단계와, 포토마스크 공정을 이용하여 트렌치 패턴을 형성하면서 산화막(5), 질화막(4), 열산화막(3), 에피택셜층(2), 매몰층(1) 및 실리콘층을 건식식각하여 트렌치(7)를 형성하고, 채널정지용 이온 주입영역(6)을 형성하는 단계의, 맨 위의 산화막(5)을 제거한 후 트렌치 산화막(8)과 산화막층(8a)을 형성하는 단계와 질화막(4)이 노출되도록 산화막층(8a)을 식각하고 포토마스크 공정을 이용하여 필드 영역을 제외한 부분에 감광막(9)을 형셩하는 단계와, 필드 영역의 질화막(4)와 열산화막(3) 및 에피택셜층(2)을 식각으로 제거하고 상면에 산화막(10), 질화막(11) 및 감광막(12)을 차례로 증착하는 단계와, 감광막(12), 질화막(11), (4), 산화막(10) 및 열산화막(3)을 식각하여 에피택셜층(2)과 트렌치 산화막(8) 및 산화막(10)의 상면이 평탄하게 노출되도록 하는 단계들에 의하여 공정이 진행됨을 특징으로 하는 트렌치를 이용한 소자간 격리방법.
- 제1항에 있어서 질화막(11)의 상면에 도포되는 감광막(12)은 점도가 낮은 물질을 사용하여 상단부에 도포되는 감광막(12)의 두께(A)가 하단부에 도포되는 감광막(12)의 두께(B)보다 낮아지도록 하고 결화막(11)과 산화막(10)을 식각함으로써 상면이 평탄해지도록 한 트렌치를 이용한 소자간 격리방법.
- 제1항에 있어서, 두 트렌치(7)의 사이인 필드영역의 폭이 넓은 경우에는 그 사이에 트렌치(17)를 추가로 형성하여 감광막(12)을 도포할때 산화막(8a, 18a)의 단차(E)에 대한 폭(F)을 조절하면서 식각시 상면이 평탄해지도록 한 트렌치를 이용한 소자간 격리방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900003823A KR920007356B1 (ko) | 1990-03-21 | 1990-03-21 | 트렌치(trench)를 이용한 소자간 격리방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900003823A KR920007356B1 (ko) | 1990-03-21 | 1990-03-21 | 트렌치(trench)를 이용한 소자간 격리방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910017618A KR910017618A (ko) | 1991-11-05 |
KR920007356B1 true KR920007356B1 (ko) | 1992-08-31 |
Family
ID=19297221
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900003823A KR920007356B1 (ko) | 1990-03-21 | 1990-03-21 | 트렌치(trench)를 이용한 소자간 격리방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR920007356B1 (ko) |
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1990
- 1990-03-21 KR KR1019900003823A patent/KR920007356B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR910017618A (ko) | 1991-11-05 |
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