KR920007137B1 - Automatic and manual switching circuit of dual systems - Google Patents

Abstract

The switching unit is for selecting usable CPU automatically or manually according to error detection signal of a CPU. The circuit includes a first and a second inverter (INV1,INV2) for inverting a first and a second fault detection signal (ERR.B, EPR.B) generated by a first and a second CPU, a second and a third LED (LED2,LED3) for displaying fault of CPU, a first switch (SW1) for selecting auto or manual switching mode, a first LED (LED1) for displaying auto switching mode, a first and a second logic units (G1,G2) for operating mode selection signal and the fault detection signals, a J/K flip-flop (FF) for generating CPU change control signal, and a second and a third switches (SW2,SW3) for applying output signals of the logic gates to a set and a reset terminals of the J/K flip-flop (FF).

Description

Automatic and manual switching device of redundant circuit

1 is a circuit diagram of the present invention.

2 is an operational waveform diagram of the present invention.

* Explanation of symbols for main parts of the drawings

FF: flip-flop LED1-LED5: light emitting diode

R1-R9: Resistor SW1, SW3: Pushbutton switch

INV1-INV3: Inverter BUF1-BUF2: Three-State Buffer

C1, C2: condenser

The present invention relates to a redundancy control circuit of a central processing unit in a private exchange, and more particularly, to a central processing unit redundancy circuit which can automatically or manually select an available central processing unit according to an error determination signal state of each central processing unit. It relates to an automatic and manual switching device.

In general, when the central processing unit of the private exchange has a redundant structure, if the user selects and operates one central processing unit, the other central processing unit is in a standby state. Therefore, if the central processing unit is redundant with, for example, the central processing unit A and the central processing unit B, and the central processing unit A which is in operation causes a failure, the user may use the central processing unit B which is in standby to continue the desired work. Can be performed. However, in the conventional case, since a user selects a normal central processing unit by directly grasping a failure of each of the central processing units, there is a disadvantage in terms of work efficiency.

Accordingly, an object of the present invention is to provide an automatic and manual switching device of a redundant circuit for automatically determining a failure of each central processing unit of a redundant central processing unit and automatically switching to a central processing unit that can operate normally.

It is still another object of the present invention to provide an automatic and manual switching device of a redundant circuit that indicates whether each central processing unit of a redundant central processing unit is broken and automatically displays a newly selected central processing unit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of the present invention, in which the first and second inverters INV1 and INV2 which invert the first and second failure determination signals ERR. A and ERR. B generated from the central processing units A and B, respectively. ) And second and third light emitting diodes LED2 and LED3 which are turned on according to the output states of the first and second inverters INV1 and INV2 to indicate whether the central processing units A and B have failed. Alternatively, a first switch SW1 for selecting the manual switching mode, a first light emitting diode LED1 that is turned on when the first switch SW1 is selected for the automatic switching mode, and a mode selection signal of the first switch SW1. And first and second logic gates G1 and G3 for logically combining the first and second failure determination signals ERR.A and ERR.B, respectively, and the two CPUs A under predetermined control. And a J / K flip-flop FF for generating a B switching control signal and the flip-flop for outputting the first and second logic gates G1 and G3 in an automatic mode, respectively. The second and third switches SW2 and SW3 applied to the reset stage R and the set stage S of the FF and the central processing unit A or B switching control signal, respectively, Fourth and fifth light emitting diodes (LED4, LED5) indicating that the switch to the device A or B, and the CPU A and B switching control signals are amplified, respectively, to generate the central processing unit A or B selection signal. A logic combination of the first and second tri-state buffers BUF1 and BUF2, the mode selection signal of the first switch SW1, and the first and second failure determination signals ERR.A and ERR.B. A first exclusive OR gate G2, a third inverter INV3 for inverting the output of the first exclusive OR gate G2, one end of which is grounded, and the other end of which receives the third inverter INV3 output and another The first stage is under software control and the signal level is determined. First and second peripheral logic gates G4 for generating a clock signal to control the flip-flop FF, and first and third peripheral circuit protections according to operations of the second and third (pushbutton) switches SW2 and SW3; Second capacitors C1 and C2 and a plurality of resistors R1-R9 are formed.

2 is an operation waveform diagram according to the present invention, 2a) is an automatic switching mode selection signal generated from the first switch SW1, 2b) is a first failure determination signal (ERR.A) waveform, and 2c). Is the first logic-sequence gate G1 output waveform, and 2d is the central processing unit B selection signal SEL.B.

The present invention will be described in detail based on the above configuration.

Assuming that the central processing unit A of the two CPUs has a failure during operation and outputs a fault determination signal ERR. From the central processing unit B, a second failure determination signal ERR.B in a low state is output. Therefore, as a result of the first failure determination signal EER.A being inverted through the first inverter INV1, the cathode of the second light emitting diode LED2 is turned low to turn on the second light emitting diode LED2. This indicates that central processing unit A has failed.

On the other hand, the d and e terminals of the first switch SW1 are connected to select the automatic mode, and the b and g terminals of the second and third switches SW2 and SW3 are connected to the c and h terminals, respectively, to select the automatic mode. In this case, (the user arbitrarily adjusts the state of the first to third switches SW1 to SW3.) Based on the connection state of the first switch SW1 to the first light emitting diode LED1. At the same time as the cathode stage is turned low, the first light emitting diode LED1 is turned on to indicate that the mode is capable of automatic switching. In addition, one input terminal of each of the first and second logic gates G1 and G3 and one input terminal of the noah gate G2 are brought into a low state. Therefore, as described above, the first logic gate G1 generates an output signal having a low state because both input terminals are in a roll state. The output of the first logical sum gate G1 in the low state is applied to the reset bar (R) terminal of the JK flip-flop FF through the c and b terminals of the second switch SW1. As a result, the JK flip-flop FF is reset to a low state to the non-inverting output terminal Q, and the fifth light emitting diode LED5 having a cathode connected to the non-inverting output terminal Q is turned on so that the user can perform central processing. In addition, the low-state signal generated from the non-inverting output terminal Q is input to the second tri-state buffer BUF2 and amplified to generate the central processing unit B selection signal. do.

On the other hand, a second or less output state is determined according to the state of the signal level applied to the first and second failure determination signal (ERR.A, ERR.B) and (d) of the first switch (SW1). The output of the gate G2 is inverted through the third inverter INV3 and then applied to the other input terminal of the exclusive OR gate G4 having one input terminal grounded.

Here, the exclusive OR gate G4 supplies a clock signal to the J / K flip-flop FF and has another input terminal SEL to enable not only hardware switching but also software switching. The other input terminal SEL should always be kept high when switching is required.

In conclusion, the failure determination signal (ERR.A, ERR.B) state of the central processing unit A and the central processing unit B and the selection of the central processing unit according to the following are shown in Table 1 below.

Here, the failure determination signals ERR.A and ERR.B generated from the respective central processing units are in a "high" state at the time of failure.

TABLE 1

^* 1: Both CPUs can operate normally. In this case, it is assumed that CPU A is given priority as an initial condition.

^* 2: Ignore the case because both CPUs are faulty.

As described above, it is possible to switch to the central processing unit that is normally operating instead of the failed central processing unit according to the failure status of the central processing unit of the central processing unit of the redundant structure, thereby improving the reliability and maintenance of the product. The effect which becomes easy is acquired.

Claims (1)

An automatic and manual switching device of a central processing unit having a redundant structure of a private exchange, comprising: inverting the first and second failure determination signals ERR.A and ERR.B generated from the central processing units A and B, respectively; Second and third light emitting diodes lit according to the output states of the first and second inverters INV1 and INV2 and the first and second inverters INV1 and INV2 to indicate whether the CPUs A and B have failed. (LED2, LED3), the first switch (SW1) for selecting the automatic or manual switching mode, the first light emitting diode (LED1) is turned on when the first switch (SW1) is selected for the automatic switching mode, and the first First and second logic gates G1 and G3 for logical combination of the mode selection signal of the switch SW1 and the first and second failure determination signals ERR.A and ERR.B, respectively, and predetermined control A J / K flip-flop (FF) for receiving the two central processing units A and B switching control signals and the first and second in the automatic mode. Second and third switches SW2 and SW3 for applying the sum gates G1 and G3 output to the reset end R and the set end 5 of the flip-flop FF, respectively, and the central processing unit A. Alternatively, the fourth and fifth light emitting diodes LED4 and LED5 indicating the switching to the central processing unit A or B are turned on according to the state of the B switching control signal, respectively, and the central processing unit A and B switching control signals are predetermined. First and second tri-state buffers BUF1 and BUF2 that amplify to generate a central processing unit A or B selection signal, a mode selection signal of the first switch SW1 and the first and second failure determination signals. A first exclusive OR gate G2 for logical combination of (ERR. A, ERR. B), a third inverter INV3 for inverting the output of the first exclusive OR gate G2, and one end is grounded and the other end is Inputs the third inverter (INV3) output and the other end is under software control to determine the signal level. Is automatic and manual control device of the redundancy circuit, characterized by configured to according to the state of the three input terminals singgi generating a clock signal in a predetermined state to the second exclusive OR gate (G4) for controlling the flip-flop (FF).

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