KR920005643A - Synchronization Generation Circuit of Still Image Telephone - Google Patents

Abstract

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Description

Synchronization Generation Circuit of Still Image Telephone

As this is a public information case, the full text was not included.

2 is a circuit diagram according to the present invention.

3 is an operation waveform diagram of each part of FIG.

Claims (3)

A synchronization generating circuit of a still picture telephone, comprising: a clock generator (10) for generating a predetermined clock signal, a divider (20) for dividing and outputting four clock signals of the clock generator (10); The horizontal synchronization generator 30 generates a horizontal synchronization signal so that the clock signal divided by the main unit 20 is a multiple of the clock signal, and the output signal of the horizontal synchronization generator 30 is inputted as a clock. And a vertical synchronizing signal generator (40) for generating a vertical synchronizing signal so as to be a multiple of the synchronizing signal. The horizontal synchronization generating unit 30 inputs the output of the division unit 20 to the first clock stage CLK1 and outputs a counting value to the output terminals 1Q0-1Q3 and 2Q0-2Q3. The output terminal 1Q3 inputs the first counter 31 connected to the second clock stage CLK2 and the counting values of the output terminals 1Q0 and 2Q0 of the first counter 31, and output terminals 1Q0-1Q3 and 2Q1. An AND gate AN2 for inputting a counting value of -2Q3) through the inverters I4-I9 to output a logic value, and a horizontal synchronization signal for inputting a logic value of the AND gate AN2 to the clock stage CLK. A flip-flop 32 for outputting a signal and a counting signal input to the output terminals 1Q2 and 2Q1-2Q3 of the first counter 31 while simultaneously inputting the divided signal of the division unit 20 through the inverter I3. And an AND gate (AN1) for generating a clear signal of the first counter (31) and the flip-flop (32) by inputting a value. The method of claim 1, wherein the vertical synchronizing unit 40 inputs the output signal of the horizontal synchronizing unit 30 to the third clock stage (CLK3) to output the counting value to the output terminal (1Q0-1Q3, 2Q0-2Q3) A second counter 41 connected to the fourth clock stage CLK4 and a count value outputted to the output terminal 2Q3 of the second counter 41 to the clock stage CLK. The counting value outputted to the output terminals 1Q2-1Q3 and 2Q0-2Q3 while inputting the counting value output to the third counter 43 and the output counters 1Q0-1Q1 of the second counter 41. Is inputted through the inverters I12-I18 and inputs the counting output value of the third counter 43 to output a logic value, and the logic value of the AND gate AN4 is input to vertical synchronization. A flip-flop 42 for outputting a signal, a counting value output to the output terminals 1Q1-1Q2 of the second counter 41, and a count output from the third counter 43. Value and the output value of the horizontal synchronization generator 30 through the inverter I11 to the AND gate AN3 for generating a clear signal of the second to third counters 41 and 43 and the flip-flop 42. And a synchronization generating circuit. ※ Note: The disclosure is based on the initial application.