JPS62126371A - Test signal generating circuit of digital circuit - Google Patents

Abstract

PURPOSE:To make it possible to take out (n) arbitrary test signals from one input line, by a simple circuit constituted so that a serial input is outputted while shifted to parallel output and this parallel output is latched by a carrier signal at every (n-1) (n is an integer of 3 or more) to be outputted. CONSTITUTION:A fundamental clock signal is applied to an input terminal I2 and a serial input pulse changing at the cycle of the fundamental clock signal is applied to an input terminal I1. Signals shifted by one cycle of the fundamental clock signal are obtained in the outputs Q1-Qn of a shift register S1. That is, (n) serial data arbitrarily inputted to the input terminal I1 are outputted as (n) parallel test signal groups. Hereinafter, the same operation is repeated in the second, third and fourth times to output parallel test signal groups.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal generation circuit for forcibly inputting an arbitrary signal when testing a digital circuit, and is particularly effective in cases where a large number of test terminals cannot be provided. This invention relates to a circuit that generates a test signal.

〔overview〕

In a test signal generation circuit for a digital circuit that sends multiple test signals to the digital circuit to be tested, the serial input is shifted to a parallel output, which is then latched with a carry signal every n-1 and output. This makes it possible to extract n arbitrary test signals from one input line using a simple circuit.

[Conventional technology]

Conventionally, this type of test signal generation circuit has been realized by a parallel bit input decoding circuit, and by configuring m input terminals (m = 2.3, 4, etc.), 2''' It provided a test signal.

[Problem that the invention seeks to solve]

Since the conventional test signal generation circuit described above is composed of a decoder, it always requires two or more human power branch lines, and it is not possible to supply test signal output with two or more lines active at the same time. There were drawbacks.

An object of the present invention is to extract n arbitrary test words from one input line using a simple circuit.

[Means for solving problems]

The test signal generation circuit for a digital circuit of the present invention includes a shift register having an n-bit (n is an integer of 3 or more) parallel output, and a shift register that counts clock signals and outputs a carry output every time (n-1) is counted. The present invention is characterized in that it includes a counter for sending data, and n flip-flops for launching and outputting the parallel output of the shift register using the carry output of the counter.

(Operation) The serial human input signal is shifted one period at a time by the clock signal in the shift register and outputted as n parallel signals.The counter outputs a carry signal every time it counts (n - 1) clocks. , n flip-flops latch the parallel signal output of the shift register and output it as a group of n parallel test signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a logic circuit according to an embodiment of the present invention, and FIG. 2 is a time chart illustrating signals of the logic circuit of FIG.

First, to explain the configuration of this test signal supply circuit with reference to Fig. 1, the symbol 'I+z+13 is an input terminal. 11 is the serial input of the test signal, I2 is the basic clock signal input, and I3 is the input terminal. The reset signal input is input. Symbol S1 is the output Q1~Q, (n=3
．． This is a serial input/parallel output shift register with 4.5...).

Symbol C1 is an (n-1) base synchronous counter;
When one clock signal is counted, the carry signal is sent from the carry terminal. F1 to F7 are D-type flip-flops that use the Q, -Q, and outputs of shift register S1 as inputs, and the carry signal of counter C1 as their clock input, and their outputs are output to output terminals 100, ~-〇-0. be done.

Note that a signal obtained by inverting the clock signal input of the shift register SI is supplied to the clock input of the counter C1, and the inverted output (CRY) of the counter C1 is sent to the flip-flop F,
~ Connected to F0's clock power. In addition, I3 is a shift register s1, a counter C1, a flip-flop F
It is connected to the reset signal input (R) of 1 to F, l.

The operation of this embodiment circuit will be explained according to FIG. A basic clock signal is applied to the input terminal rz, and a serial input pulse that changes with the period of the basic clock signal is applied to the input terminal 11. Q of shift register S1
1 to Q, a signal shifted by one period of the basic clock is obtained at the output.

When the reset signal supplied to the input terminal I falls, the (n-1)-adjustable counter C1 starts operating from the fall of the first basic clock.

The first parallel shift data (Q l"Q , ,) output from the shift register S is sent to the flip-flop F,
-F, is latched at the rising edge (CRY) of the inverted carry output of the (n-1)-adc synchronous counter C, and the first test data signal is output to the output terminals 100 and 100, respectively. Output. That is, input terminal I
, n pieces of serial data arbitrarily entered manually are outputted as a group of n parallel test signals. Thereafter, the same operation is repeated for the second, third, and fourth times, and a parallel test signal group is output.

〔Effect of the invention〕

As explained above, according to the present invention, n arbitrary test signals can be taken out using a simple circuit, and simultaneous operation setting of a group of the test signals can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. 1+, Ez, 1. +...Input terminal, SL...Shift register, C1...Counter, F1 to F0...Flip-flop, -〇-1 to U,...Output terminal.

Claims (1)

[Claims] (1) A shift register (S_1) with an n-bit (n is an integer of 3 or more) parallel output, and a counter (C_1) that counts clock signals and sends out a carry output every time it counts (n-1). and n flip-flops (F_
1 to F_n).