KR920005630A - Digital still video recorder player with PIP function - Google Patents

Digital still video recorder player with PIP function Download PDF

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Publication number
KR920005630A
KR920005630A KR1019900013525A KR900013525A KR920005630A KR 920005630 A KR920005630 A KR 920005630A KR 1019900013525 A KR1019900013525 A KR 1019900013525A KR 900013525 A KR900013525 A KR 900013525A KR 920005630 A KR920005630 A KR 920005630A
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KR
South Korea
Prior art keywords
signal
screen
output
switch
data
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Application number
KR1019900013525A
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Korean (ko)
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KR930003961B1 (en
Inventor
정병춘
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강진구
삼성전자 주식회사
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Priority to KR1019900013525A priority Critical patent/KR930003961B1/en
Publication of KR920005630A publication Critical patent/KR920005630A/en
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Publication of KR930003961B1 publication Critical patent/KR930003961B1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/76Television signal recording

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

내용 없음.No content.

Description

PIP기능을 가지는 디지탈 스틸비디오 레코더 플레이어Digital still video recorder player with PIP function

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 PIP기능을 가지는 스틸비디오 플레이어의 블럭도.1 is a block diagram of a still video player having a PIP function according to the present invention.

제2도 및 제3도는 자화면 선택시의 서브-샘플링 동작상태 및 자화면 크기 상태도.2 and 3 are diagrams showing the sub-sampling operation state and the sub picture size state when the sub picture is selected.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 메모리카드 12 : 카드 인터페이스10: memory card 12: card interface

14 : 데이터 복원회로 16 : 제1스위치14 data recovery circuit 16 first switch

18 : 판정회로 20 : 보간회로18: judgment circuit 20: interpolation circuit

22 : CPU 24 : 키보드22: CPU 24: keyboard

26 : 표시부 32,34,58,60 : 제2,제3,제4,제5스위치26: display part 32, 34, 58, 60: second, third, fourth, fifth switch

36 : 선택회로 38,40 : 제1, 제2데이터 콘트롤로36: selection circuit 38, 40: first and second data control

42,50 : 제1,제2신호발생기 44,46 : 제1,제2프레임 메모리42,50: first and second signal generator 44,46: first and second frame memory

48 : 프레임 메모리 콘트롤러 52,54 : 제1,제2D/A변환기48: frame memory controller 52,54: first, second D / A converter

56 : 윈도우발생기 62 : 휘도레벨56: window generator 62: luminance level

64 : 엔코더64: encoder

Claims (1)

디지탈 스틸 비디오 카메라에서 처리하여 된 비디오 데이타를 저장하고 있는 메모리카드(10)와, 상기 메모리카드(10)에 접속되어 있으며, 영상선택 신호와 압축모드 신호를 입력하여 상기 메모리카드(10)로 부터 영상데이터를 읽고 이를 보간 출력하는 기록정보 보간 출력회로(100)을 구비하여 PIP기능을 가지는 디지탈 스틸 비디오 레코더 플레이어에 있어서, 모화면(Main Screen)과 자화면(Sub)선택신호 및 화면크기 선택신호등을 입력하는 키보드(24)와, 상기 키보드(24)를 통해 입력되는 명령 신호에 의해 상기 기록정보 보간 출력회로(100)을 제어하여 상기 메모리카드(10)의 데이타를 읽어 압축모드를 판정하고, PIP기능선택신호와 서브화면 선택신호, 출력 제어신호를 출력하는 CPU(22)와, 상기 CPU(22)의 처리 상태를 표시하는 표시부(26)와, 상기 기록정보 보간 출력회로(100)의 출력단자에 접속되어 모/자화면 선택신호에 따라 스위칭하여 모화면과 자화면을 스위칭하는 제2스위치(32)와, 상기 제2스위치(32)의 자화면 출력단자에 접속되어 자화면 크기 선택신호에 따라 스위칭되어 자화면의 크기를 선택하는 제3스위치(34)와, 상기 CPU(22)의 PIP기능 선택신호를 입력하여 상기 제2,제3스위치(32)(34)에 모/자화면 선택신호와 자화면 선택신호를 제공하는 선택회로(150)와, 상기 제3스위치(34)의 각각의 출력단자에 접속되어 있으며 제1,제2인이에블신호에 의해 입력된 화상데이터를 제1크기의 화면 데이터와 제2크기의 화면 데이터로 각각 서브 샘플링 출력하는 제1,제2데이터 콘트롤러(38),(40)와, 상기 CPU(22)와 제1, 제 2 데이터 콘트롤러(38)(40) 사이에 접속되어 상기 CPU(22)의 서브화면 선택신호에 따라 상기 제1 혹은 제 2 데이터 콘트롤러(38)(40)에 제1,제2인에이블 신호를 제공하여 동작시키는 제1신호발생기(42)와, 상기 제2스위치(32)의 자화면 출력단자와 상기 제1,제2데이터 콘트롤러(38)(40)의 출력단자에 각각 접속되어 소정제어에 의해 각각 입력되는 모화면 및 자화면의 화상데이터를 저장하고 리이드 출력하는 제1, 제2프레임 메모리(44),(46)과, 상기 CPU(22)의 출력제어 신호에 의해 메모리 제어신호와 윈도우 제어신호와 엔코더 제어신호를 발생하는 제2신호발생기(50)와, 상기 제2신호발생기(50)와 제1,제2프레임 메모리(44)(46)사이에 접속되어 상기 메모리 제어신호에 의해 상기 제1,제2프레임 메모리(44)(46)의 입출력을 제어하는 프레임 메모리 콘트롤러(48)와 상기 제2신호발생기(50)의 윈도우 제어신호에 따라 PIP의 윈도우를 발생하는 윈도우 신호발생기(36)와, 상기 제1, 제2프레임 메모리(44)(46)의 출력을 각각 디지탈-아나로그의 변환하는 제1,제2D/A(52)(54)와, 상기 제1,제2 D/A변환기(52)(54)의 출력을 상기 윈도우 신호발생기(56)의 출력에 따라 선택스위칭 출력하는 제4스위치(58)와, 모화면과 자화면 경계선의 밝기를 설정하는 경계신호를 출력하는 상기 윈도우 신호발생기(56)의 출력에 따라 스위칭하여 출력하는 제5스위치(60)와, 상기 제5스위치(60)의 출력을 상기 제2신호발생기(50)의 출력에 의해 엔코딩하여 모니터링신호로 출력하는 엔코더(64)로 구성됨을 특징으로 하는 PIP기능을 가지는 디지탈 스틸 비디오 레코더 플레이어회로.A memory card 10 that stores video data processed by a digital still video camera and a memory card 10 connected to the memory card 10, and inputs an image selection signal and a compression mode signal from the memory card 10; In a digital still video recorder player having a PIP function having a recording information interpolation output circuit 100 for reading and interpolating image data, the main screen and sub screen selection signals, screen size selection signals, and the like. The recording information interpolation output circuit 100 is controlled by a keyboard 24 for inputting a command and a command signal input through the keyboard 24 to determine a compression mode by reading data of the memory card 10, CPU 22 for outputting the PIP function selection signal, the sub-screen selection signal, and the output control signal, a display unit 26 for displaying the processing status of the CPU 22, and the recording information interpolation output. A second switch 32 connected to an output terminal of the furnace 100 and switching according to a mother / child screen selection signal to switch the mother screen and the child screen, and to the child screen output terminal of the second switch 32 And a third switch 34 which selects the size of the sub picture by switching according to the sub picture size selection signal, and inputs the PIP function selection signal of the CPU 22 to the second and third switches 32 and 34. Is connected to the respective output terminals of the third switch 34 and the selection circuit 150 for providing the mother / sub picture selection signal and the sub picture selection signal to the first and second enable signals. First and second data controllers 38 and 40 for sub-sampling and outputting input image data into screen data of a first size and screen data of a second size, respectively; and the CPU 22, first, and first Two data controllers 38 and 40 connected between the first and second data controls according to the sub-screen selection signal of the CPU 22; A first signal generator 42 which operates the first and second enable signals by providing the first and second enable signals to the plurality of detectors 38 and 40, the sub picture output terminal of the second switch 32, and the first and second data. First and second frame memories 44 and 46 which are connected to the output terminals of the controllers 38 and 40, respectively, and store and lead-out image data of the mother screen and the mother screen respectively inputted by predetermined control; And a second signal generator 50 for generating a memory control signal, a window control signal, and an encoder control signal according to the output control signal of the CPU 22, the second signal generator 50, and the first and second frames. Frame memory controller 48 and the second signal generator 50 connected between the memory 44 and the 46 to control input and output of the first and second frame memories 44 and 46 by the memory control signal. A window signal generator 36 for generating a window of the PIP according to the window control signal of The outputs of the first and second D / A converters 52 and 54 for digital-to-analog conversion of the outputs of the Switching according to the output of the window switch generator 56 for outputting a selective switch according to the output of the window signal generator 56, and a boundary signal for setting the brightness of the border between the parent screen and the sub-screen And the encoder 64 for encoding the output of the fifth switch 60 and the output of the fifth switch 60 by the output of the second signal generator 50 to output the monitoring signal. Digital still video recorder player circuit with PIP function. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900013525A 1990-08-30 1990-08-30 Digital still video recorder player KR930003961B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900013525A KR930003961B1 (en) 1990-08-30 1990-08-30 Digital still video recorder player

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013525A KR930003961B1 (en) 1990-08-30 1990-08-30 Digital still video recorder player

Publications (2)

Publication Number Publication Date
KR920005630A true KR920005630A (en) 1992-03-28
KR930003961B1 KR930003961B1 (en) 1993-05-17

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Application Number Title Priority Date Filing Date
KR1019900013525A KR930003961B1 (en) 1990-08-30 1990-08-30 Digital still video recorder player

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