KR930003961B1 - Digital still video recorder player - Google Patents

Abstract

The player for displaying the main screen and the sub screen simultaneously comprises: a key board (24) inputting the signal for selecting the main screen, the sub screen and the screen size; a CPU (22) outputting the control signal and the signal for selecting the PIP function and the sub screen; a section (26) displaying the processing state of CPU; a second switch (32) switching the main and sub screen according to the selecting signal of the main/sub screen; a third switch (34) selecting the sub screen size; a selecting circuit (150) providing the main/sub screen selecting signal to the second and the third switches (32,34) by inputting the PIP function selecting signal; a first and second controllers (38,40).

Description

Digital still video recorder player with PIP function

1 is a block diagram of a still video player having a PIP function according to the present invention.

2 and 3 are diagrams showing the sub-sampling operation state and the sub picture size state when the sub picture is selected.

* Explanation of symbols for main parts of the drawings

10: memory card 12: card interface

14 data recovery circuit 16 first switch

18: judgment circuit 20: interpolation circuit

22: CPU 24: keyboard

26: display part 32, 34, 58, 60: second, third, fourth, fifth switch

36: selection circuit 38, 40: first and second data control

42,50: first and second signal generator 44,46: first and second frame memory

48: frame memory controller 52,54: first, second D / A converter

56: window generator 62: luminance level

64: encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital still video recorder player, and in particular, reads image information recorded on a memory card, selects and plays a desired video as a main screen or a sub screen, The present invention relates to a digital recorder player capable of switching the size of a sub picture to a desired size.

In general, a digital still video recorder player is a device for reproducing image information obtained by digitally recording a still image on a memory card by performing signal processing on photoelectrically converted image information by a CCD (solid-coupled device) in a still video camera. Say. In other words, a digital still video recorder player box reads image information recorded on a memory card and displays it on a monitor.

The conventional still video recorder player having the above function does not have various screens, for example, picture in picture (PIP) function, by only reading information recorded on a memory card and playing back still images. The sub screen cannot be displayed together.

Accordingly, an object of the present invention is to provide a digital still video recorder player that reads image information recorded in a memory device, displays selected image data on the main screen when the user selects a desired image number, and displays the image data in a reduced or enlarged manner. Is in.

Another object of the present invention is a still video having a PIP function for displaying a PIP screen by outputting the sub-screen image data of the sub-screen image data as display data of one screen when the sub-screen video number and the sub-screen video number are selected and input. In providing a recorder player.

It is still another object of the present invention to provide a still video recorder player capable of selecting and switching a size (window) of a selected sub picture so that the sub picture can be reduced or enlarged to 1/4 or 1/9.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, which stores video data processed by a digital still video camera and is connected to a memory card 10 and the memory card 10, and inputs an image selection signal and a compression mode signal. A recording information interpolation output circuit 100 for reading image data from the memory card 10 and interpolating the same, and inputting a main screen, a sub screen selection signal, a screen size selection signal, and the like. 24 and the recording information interpolation output circuit 100 are controlled by the command signal input through the keyboard 24 to read the data of the memory card 10 to determine the compression mode, and to select the PIP function selection signal. And a central processing unit (CPU) 22 for outputting a sub-screen selection signal and a central output control signal for outputting an output control signal, a display unit 26 for displaying the processing status of the CPU 22, and the recording information. Interpolation A second switch 32 connected to an output terminal of the output circuit 100 and switching in accordance with a mother / child screen selection signal to switch the mother screen and the child screen, and to the child screen output terminal of the second switch 32. A third switch 34 connected to and switched according to a sub picture size selection signal and inputting a PIP function selection signal of the CPU 22 and the second and third switches 32 and 34. A selection circuit 150 for providing an E / S screen selection signal and a sub screen selection signal, and an output terminal of each of the third switches 34 and inputted by the first and second enable signals. First and second data controllers 38 and 40 for subsampling and outputting image data into screen data of a first size and screen data of a second size, respectively;

Connected between the CPU 22 and the first and second data controllers 38 and 40 and connected to the first or second data controllers 38 and 40 according to the sub-screen selection signal of the CPU 22. A first signal generator 42 for providing and operating first and second enable signals;

Image data of the mother screen and the child screen, which are connected to the mother screen output terminal of the second switch 32 and the output terminals of the first and second data controllers 38 and 40, respectively, are entered by predetermined control. First and second frame memories 44 and 46 for storing and reading out the lead,

A second signal generator 50 for generating a memory control signal, a window control signal and an encoder control signal according to the output control signal of the CPU 22, and the second signal generator 50 and the first and second frame memories. A frame memory controller 48 connected between (44) and (46) to control input / output of the first and second frame memories (44) and (46) by the memory control signal;

According to the window control signal of the second signal generator 50, the window signal generator 36 for generating a window of the PIP and the outputs of the first and second frame memories 44 and 46, respectively, First and second digital-to-analog converters (hereinafter referred to as D / A converters) 52 and 54,

A fourth switch 58 for selectively switching and outputting the outputs of the first and second D / A converters 52 and 54 according to the output of the window signal generator 56, and the brightness of the border between the mother and child screens; A fifth switch 60 for switching and outputting according to the output of the window signal generator 56 for outputting a boundary signal to be set;

The encoder 64 encodes the output of the fifth switch 60 by the output of the second signal generator 50 and outputs the result to a monitor (not shown).

In the configuration of FIG. 1, the write information interpolation output circuit 100 is connected with the memory card to read a stored data (hereinafter referred to as card I / F) 12 and inputs a compression mode signal. A determination circuit 40 for determining a mode, a data restoration circuit 14 for restoring the output data of the card I / F 12 to the original image according to the output of the determination circuit 140, and the determination circuit 14 A first switch 16 for selecting an output of the card I / F 12 or the data recovery circuit 14 according to an output of the first switch 16 and a selected output of the first switch 16 of the determination circuit 14; The interpolation circuit 20 interpolates the subsampled image data according to the output to a state before sub-sampling.

FIG. 2 is an exemplary view of an operation when the camera uses a CCD (solid image pickup device) consisting of 768 pixels horizontally and 488 vertical lines. FIG. 2A is a diagram illustrating the operation of the first data controller 38. FIG. Sub-Sanping operation of 1 / a is shown (2b), and the size of the sub picture is shown.

FIG. 3 is an exemplary diagram when the same CCA (solid-state image pickup device) as shown in FIG. 2 is used in the camera, and FIG. 3A shows the size of the sub picture at the time of 1/4 subsampling in the second data controller 4.

An example of the operation of FIG. 1 will be described in detail with reference to FIGS. 2 and 3. When the memory card 10 in which image information is recorded in FIG. 1 is inserted now, the CPU 22 reads and reads mode information recorded in the memory card 10 through the card I / F 12. At this time, if the user designates a desired file number (video signal) by operating the keyboard 24, the CPU 22 assigns the designated video number to the card I / F 12. The card I / F 12 generates an address corresponding to the video signal, reads out image data from the memory card 10 one by one, and outputs the data to the CPU 22. At this time, the selected image data recorded in the memory card 10 is transferred to the data restoration circuit 14 and the first switch 16 through the card I / F 12. On the other hand, the CPU 22 reads the compression mode of the corresponding image data of the memory card 1 designated by the keyboard 24 via the card I / F 12 and transmits it to the determination circuit 18.

The determination circuit 18 determines the compression mode signal to control the data recovery circuit 14, the first switch 16, and the interpolation circuit 20. At this time, the image data is restored to the original image by the data restoration circuit 14 through the card I / F 12. That is, the mode signal output from the card I / F 12 is input to the determination circuit 18 through the CPU 22, and the mode is determined by the determination circuit 18. In accordance with the determination result of the determination circuit 18, the state of the first switch 16 is switched and at the same time, the operation of the data recovery circuit 14 and the auxiliary circuit 20 is also switched and controlled. The information determined by the determination circuit 18 is a compression mode selected at the time of recording by the camera. For example, when the image designated by the keyboard 24 is compressed to 1/4, the CPU 22 sends this information to the determination circuit 18, and the determination circuit 18 determines the information to determine the data. ) Expands the data by 4 times so as to restore the original image. In addition, if the sub-sampling is performed at 1/2 in the camera, the interpolation circuit 20 interpolates the same to the original image. If the image selected by the keyboard 24 is data without signal compression in the high quality mode, the determination circuit 18 switches the first switch 16 to immediately output the output of the card I / F 12 to the interpolation circuit ( 20). The interpolation circuit 20 interpolates the sub-sampling video data to the state before sub-sampling in the camera.

Control of the path according to the above-described mode is as follows. The mode signal output from the card I / F 12 is input to the determination circuit 18 via the CPU 22, and the compression mode is determined by the determination circuit 18. In accordance with the determination result of the determination circuit 18, the state of the first switch 16 is switched, and the operation of the data recovery circuit 14 and the interpolation circuit 20 is also switched. For example, when the PIP function is not selected and only an image number is input, the CPU 22 outputs a sub picture selection signal to the selection circuit 36 and outputs an output control signal to the control signal generator 10. At this time, the selection circuit 36 switches the second switch 32 so that the output of the interpolation circuit 20 is input to the first frame memory 44.

In addition, the second signal generator 50 inputting the output control signal from the CPU 22 outputs the memory control signal to the frame memory controller 48, and the frame memory controller 48 writes a write signal and an address. Outputs

Therefore, the output of the interpolation circuit 20 is joined to the first frame memory 44. When writing of image data is completed in the first frame memory 44, the frame memory controller 48 outputs a read control signal and an address to output the stored data. The data output from the first frame memory 44 is converted into an analog signal by the first D / A converter 52 and then the contacts C and D of the fourth and fifth switches 58 and 60. Is input to the encoder 64. At this time, the encoder 64 encodes the input mother screen video signal and outputs it to the monitor so that the mother screen is displayed.

When the sub-screen selection signal and the size selection signal for executing the PIP function are input in the state where the main screen is displayed as described above, the CPU 22 analyzes this and the card I / F 12 described above. The designated video signal (sub picture selection number) is assigned as described above, and is input to the PIP function selection signal, the sub picture selection circuit 36 and the first signal generator 42, respectively. The CPU 22 outputs the PIP function output control signal to the control signal generator 50.

On the other hand, the card I / F 12 inputting the video selection signal by the sub picture selection signal from the CPU 22 generates the address of the video signal by the sub picture selection, and determines the compression mode of the image data. As described above, it is input to the determination circuit 18 via the CPU 22. Therefore, the interpolation circuit 20 in the recording information interpolation output circuit 100 interpolates the video data of the screen number by the sub picture selection. At this time, the selection circuit 36 drives the second switch 32 to switch to A '. On the other hand, the switching condition of the third switch 34 is to select the size of the magnetic screen, and is switched to select 1/9, 1/4 of the area of the magnetic screen according to the input of the keyboard 24. The selection circuit 36 It is switched according to the screen size selection signal of.

For example, if the user selects 1/9 as the size of the child screen, the CPU 22 outputs a 1/9 character screen PIP function selection signal to the selection circuit 36. At this time, the selection circuit 36 switches the second switch 32 to the terminal A 'according to the input 1/9 character screen PIP function selection signal, and then switches the third switch 34 to the 1/9 character screen. In case of PIP function selection signal, switch to terminal B.

Therefore, when the user selects the size of the sub picture as 1/9, the sub picture selection image data outputted from the interpolation circuit 20 is input to the first data controller 38, so that the horizontal and vertical values are 1/9 as shown in FIG. 3 results in sub-sampling. At this time, the control of the first and second data controllers 38 and 40 is performed by the first signal generator 42, and the first signal generator 42 according to the sub-screen selection signal provided from the CPU 22. Enable the first data controller 38 or the second data controller 40.

For example, when the sub-screen selection signal output from the CPU 22 is 1/9 selection, the first data controller 38 is enabled, so that the input screen image data is output from the first data controller 38 to the second. As shown in Fig. 2A, the aspect ratio is subsampled to 1/3 to be output.

The image data of the sub picture which is compressed by 1/9 by the first data controller 38 and output is recorded in the second frame memory 46 under the control of the frame memory controller 48.

If the user selects the size of the child screen as 1/4 of the main screen or changes the size of the child screen, the CPU 22 outputs a 1/4 character PIP function selection signal to the selection circuit 36. The selection circuit 36 causes the third switch 34 to be switched to the terminal B '.

The first signal generator 42 outputs a 1/4 sub-screen selection signal to enable the first signal generator 42 to enable the second data controller 40.

Therefore, when the 1/4 character screen PIP is selected, the video signal of the child screen outputted from the terminal A 'of the second switch 32 is horizontal, as shown in FIG. 3A by the second data controller 40. The length is subsampled in half, reduced (compressed) in quarter, and then written to the second frame memory 46.

The image data of the sub picture recorded in the second frame memory 46 is ride under the control of the frame memory controller 48 under the control of the second signal generator 50 and is analyzed by the second D / A converter 54. The signal is converted into a log signal and input to the terminal C 'of the fourth switch 58.

At this time, the fourth switch 58 is switched to the terminal C 'by the window signal output from the window signal generator 56, that is, the window signal corresponding to the size of the sub picture, and is output from the second frame memory 46. Select and output the video data of the screen. At this time, the window signal generator 56 generates a window signal for compensating the boundary between the mother screen and the child screen under the control of the second signal generator 50 to switch the fourth switch 58 and the fifth switch 50. The luminance level unit 62, which provides the control signal and adjusts the brightness of the boundary portion, is selected. In other words, the fifth switch 60 is switched to the terminal D 'at the boundary between the mother screen and the child screen, and the fifth switch 60 is switched to the terminal D within the size of the selected sub screen, and the fourth Switch 58 is switched to terminal C '.

Therefore, in accordance with the synchronization of the second signal generator 50, the frame memory controller 48, and the window signal generator 56, the image data of the output sub picture is output from the second frame memory 46 through the encoder 64. An image of " parent screen + child screen " such as FIG. 2B or FIG. 3B is displayed on the monitor.

As described above, the present invention reads the image information stored in the memory card, records the image data of the main screen in the first frame memory, and sets the image data designated as the sub-screen to one-quarter of the main screen according to the size selection of the sub-screen. Alternatively, the main screen and the sub screen may be simultaneously displayed by subsampling to have a size of 1/9, detecting and writing the data to the second frame memory, and switching and outputting the stored data of the second frame memory within the data output period of the first frame memory. There is an advantage to that.

Claims (1)

A memory card 10 that stores video data processed by a digital still video camera and a memory card 10 connected to the memory card 10, and inputs an image selection signal and a compression mode signal from the memory card 10; In a digital still video recorder player having a PIP function having a recording information interpolation output circuit 100 for reading and interpolating image data, the main screen and sub screen selection signals, screen size selection signals, and the like. The recording information interpolation output circuit 100 is controlled by a keyboard 24 for inputting a command and a command signal input through the keyboard 24 to determine a compression mode by reading data of the memory card 10, CPU 22 for outputting the PIP function selection signal, the sub-screen selection signal, and the output control signal, a display unit 26 for displaying the processing status of the CPU 22, and the recording information interpolation output. A second switch 32 connected to an output terminal of the furnace 100 and switching according to a mother / child screen selection signal to switch the mother screen and the child screen, and to the child screen output terminal of the second switch 32 And a third switch 34 which selects the size of the sub picture by switching according to the sub picture size selection signal, and inputs the PIP function selection signal of the CPU 22 to the second and third switches 32 and 34. Is connected to the respective output terminals of the third switch 34 and the selection circuit 150 for providing the mother / sub picture selection signal and the sub picture selection signal to the first and second enable signals. First and second data controllers 38 and 40 for sub-sampling and outputting input image data into screen data of a first size and screen data of a second size, respectively; and the CPU 22, first, and first Two data controllers 38 and 40 connected between the first and second data controls according to the sub-screen selection signal of the CPU 22; A first signal generator 42 which operates the first and second enable signals by providing the first and second enable signals to the plurality of detectors 38 and 40, the sub picture output terminal of the second switch 32, and the first and second data. First and second frame memories 44 and 46 which are connected to the output terminals of the controllers 38 and 40, respectively, and store and lead-out image data of the mother screen and the mother screen respectively inputted by predetermined control; And a second signal generator 50 for generating a memory control signal, a window control signal, and an encoder control signal according to the output control signal of the CPU 22, the second signal generator 50, and the first and second frames. Frame memory controller 48 and the second signal generator 50 connected between the memory 44 and the 46 to control input and output of the first and second frame memories 44 and 46 by the memory control signal. A window signal generator 36 for generating a window of the PIP according to the window control signal of The outputs of the first and second D / A converters 52 and 54 for digital-to-analog conversion of the outputs of the Switching according to the output of the window switch generator 56 for outputting a selective switch according to the output of the window signal generator 56, and a boundary signal for setting the brightness of the border between the parent screen and the sub-screen And the encoder 64 for encoding the output of the fifth switch 60 and the output of the fifth switch 60 by the output of the second signal generator 50 to output the monitoring signal. Digital still video recorder player circuit with PIP function.

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