KR920005247B1 - C-bit processor of dat's digital signal processor - Google Patents

Abstract

The circuit includes a clock generating means (10) for generating first and second bit synchronizing clocks. A synchronizing signal generating means (20) generates a synchronizing signal for every n continuous clocks, and a first clock window means (30) permits m units of the first bit synchronizing clocks to be passed, each time when the synchronizing signal is generated. A counter (40) counts m units of the first bit synchronizing clocks, and a second clock window means (50) permits p units of the second bit synchronizing clocks to be passed, while a shift register (60) shifts and memorizes only the bits corresponding to the p units of the second bit synchronizing clocks.

Description

C-bit processing circuit of DSP chip for DAT

1 is a circuit diagram of one embodiment of a C-bit processing circuit according to the present invention.

2 is a view of the waveform of FIG.

* Explanation of symbols for main parts of the drawings

10: clock generating means 20: synchronization signal generating means

30: first clock window means 40: counter

50: second clock window means 60: shift register

70: register

The present invention relates to a digital audio tape (DAT) device, and more particularly, to a C-bit processor of a digital signal processor (DSP) chip.

The DAT apparatus includes a DSP chip for digital signal processing such as error detection and error correction of digital data reproduced from magnetic tape, and deinterleaving the interleaved data. This DSP performs a predetermined digital signal processing operation while exchanging data with system control means such as a microcomputer. The DSP chip receives 192 bits of C-bit signal in series from the microcomputer to control the circuits inside the chip. It is supplied serially with C-bit signal consisting of 1 pair of 192 bits. The required bit data of the 192bit data is a total of 22bit data, 16 bits from 1st to 16th, 4bits from 25th to 28th and 2bits from 29th to 30th. The circuit which attempts to take only the last 22 bits of data required by the 192 bits of data is a C-bit processor circuit.

Conventional C-bit processor method takes up to 32th bit data through 32 D-type flip-flops (D-FF) to take up to 30th bit data needed from 192 bit data serially supplied. It takes 22 bit data which is needed out of 32 bit data. Therefore, 10 unnecessary D-FFs are needed and the peripheral circuits are complicated.

An object of the present invention is to provide a C-bit processor with a simple circuit configuration in order to solve the above problems of the prior art.

Another object of the present invention is to provide a C-bit processor that is automatically reset every group.

Another object of the present invention is to provide a C-bit processor that can facilitate the circuit integration of the DSP chip.

개의 비트마다 연속하는 m개의 비트중 n개의 비트를 취출하기 위한 DAT용 DSP칩의 씨-비트처리회로에 있어서, 상기 직렬비트열에 동기된 제1 및 제2비트동기클럭을 발생하기 위한 클럭발생수단, 상기 제1비트동기클럭의 연속하는

개의 클럭마다 동기신호를 발생하기 위한 동기신호발생수단; 상기 동기신호발생시마다 상기 제1비트동기클럭중 연속하는 m개의 제1비트동기클럭만을 통과시키기 위한 제1클럭윈도우수단; 상기 연속하는 m개의 제1비트동기클럭을 계수하기 위한 카운터; 상기 카운터의 각 비트출력을 조합하여 상기 제2비트동기클럭의 연속하는 m개중 상기 n개의 비트에 동기된 클럭만을 통과시키기 위한 제2클럭윈도우수단 ; 상기 직렬비트열중 상기 제2클럭윈도우수단을 통과한 n개의 제2비트동기클럭에 대응하는 비트만을 쉬프링시키면서 기억시키기위한 쉬프트레지스터 ; 그리고 상기 쉬프트레지스터에 기억된 n개의 비트를 상기 제1클럭윈도우수단의 클럭통과 직후에 병렬로드하여 기억시키기 위한 n비트 레지스터를 구비하여서 된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a continuous

A C-bit processing circuit of a DAT DSP chip for taking out n bits of m bits consecutive for each bit, comprising: clock generating means for generating first and second bit synchronization clocks synchronized with the serial bit string; Continuous of the first bit sync clock

Synchronizing signal generating means for generating a synchronizing signal for each of the two clocks; First clock window means for passing only m consecutive first bit sync clocks among the first bit sync clocks each time the synchronization signal is generated; A counter for counting the consecutive m first bit sync clocks; Second clock window means for combining each bit output of said counter to pass only a clock synchronized with said n bits of m consecutive m bits of said second bit synchronization clock; A shift register for storing while shifting only bits corresponding to n second bit synchronous clocks having passed through said second clock window means in said serial bit stream; And n-bit registers for parallel-loading and storing n bits stored in the shift register immediately after the clock pass of the first clock window means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of one embodiment of the C-bit processing circuit according to the present invention. 2 is a timing chart of each part of FIG. In FIG. 1, the system control unit of the DAT receives the C-bits serially input to the DSP chip as a group, and receives 16 bits of 1 to 16th bits and 4 of 25 to 28th bits. It is a circuit for extracting two 29th to 30th bits, that is, 22 bits in total, and outputting them in parallel.

The clock generating means 10 generates a first bit synchronous clock ψ ₁ shown in FIG. 2 which rises every bit. In addition, this is the same one-bit synchronization clock (ψ ₁₎ and cycle the phase is 180 ° teulrimyeo duty generates a small second bit synchronizing clock (ψ _1).

The synchronizing signal generating means 20 generates the synchronizing signal SYNC shown in FIG. 2 having a pulse width of one period of the first bit synchronizing clock? _{1 for} every 192 bit group. That is, the synchronization signal SYNC descends at the first clock rising edge of the 192 first bit sync clocks ψ ₁ and rises at the second clock rising edge.

First clock window means (30) is passed through by inverting the first 32-bit synchronization clock (ψ _1), from the falling edge of the sync signal (SYNC) to said first bit synchronizing clock (ψ _1).

The counter 40 is a 5-bit binary counter for counting the 32 first bit synchronous clocks ψ ₁ that have passed through the first clock window means 30. The counter 40 is cleared at the falling edge of the sync signal SYNC and starts counting at the rising edge and holds the count value 31 until the next clear. The counter 40 is cleared at the falling edge of the sync signal SYNC and starts counting at the rising edge and holds the count value 31 until the next clear. When the count value 31 of the counter 40 is reached, the first clock window means 30 is reset at the falling edge of the 32nd clock of the second bit synchronous clock ψ ₁ so that the first bit synchronous clock ψ _1. ) Is blocked.

Accordingly, the first clock window means 30 generates the first window signal W1 as shown in FIG. Looking at the generation of the first window signal W1, first, the sync signal SYNC is set to one input terminal of the NAND gate G ₁₀ of the RS flip-flop composed of the NAND gate G ₉ (G ₁₀ ). Is supplied to the RS flip-flop at the falling edge of this synchronization signal, and the output terminal of the NAND gate G ₁₀ is maintained at " H " state. This " H " state is applied to the NAND gate G ₁₁ through the buffer B2 to allow the first bit synchronous clock ψ ₁ to pass. The clock passed is supplied to the counter 40 and counted. When the counter value 31 from the counter 40, this NOR gate (G ₆₎ (G ₇₎ and a second bit synchronizing clock which is decoded at a NAND gate (G ₈₎ and applied to the NOR gate (G ₆₎ (ψ ₂ ) it is the 32nd clock through the NAND gate (G ₈₎ 32nd clock through the NAND gate (G ₈₎ a is to be applied to the reset signal of the RS flip-flop. Accordingly, the output of the NAND gate G ₉ is in the "H" state, and the set output of the RS flip-flop is inverted from "H" to "L". Therefore, the first window signal W1 of FIG. 2 is generated at the output of the NAND gate G ₁₀ . The first window signal W1 is applied as a parallel load clock signal to a register to be described later via the buffers B2 and B3.

The second clock window means 50 stores 16 clocks from 1st to 16th of the 192 of the second bit sync clock ψ ₁ , and 6 clocks from 25th to 30th, that is, 22 clocks in total. To selectively pass, the 5 bit output of the counter 40 is combined to decode 1110X, 110XX, 0XXX to generate a second window signal W2.

₁Q₂Q₃Q₄를 NAND게이트(G3)에서 카운터(40)의 출력

_{2 3 4 4 4 2 3} The 1110X sets the 29th to 30th clock pass section, the 110XX sets the 25th to 28th clock pass section, and the 0XXXX sets the 1st to 16th clock pass section. Accordingly, the second window signal W2 outputs the counter 40 at the NAND gate G ₂ .

₁ Q ₂ Q ₃ Outputs counter ₄ from NAND gate (G3)

_{2 3 4 4 4 2 3}

The second window signal W2 gates the second bit synchronous clock ψ ₂ input through the inverter G ₁ at the NAND gate G ₅ to be the 1-16th clock and 25-30 of the 192 clocks. Only the first clock passes. These clocks are supplied to the serial load clock of the shift register described later through the buffer B1. The shift register 60 is connected in series with 22 D-type flip-flops and inputs 22 second bit synchronous clocks PCK, which are selectively output by the second clock window means 50, to be supplied in series from the system controller. For each of the 192 bit groups, the 1st to 16th bits and the 25 to 30th bits are sequentially shifted and stored.

The register 70 is composed of 22 D flip-flops and the 22 bits stored in the shift register 60 are stored at the falling edge of the first window signal W1 supplied from the first clock window means 30. Parallel read outputs 22 bits in parallel.

The clock generating means 10, the synchronizing signal generating means 20, the counter 40, the first clock window means 30, the shift register 60, and the register 70 are described by the master reset signal MRST. Reset.

As described above, in the present invention, only the desired bits are taken out while counting using a binary oscillator counter that can sufficiently include desired bits for taking out and outputting only the desired 1-16th and 25-30th bits for every 192 serial bit strings. And a shift register and a resist having a size corresponding to the desired number of bits, the circuit configuration is simplified. This makes it easier to make a one-chip of the DAT DSP.

Claims (1)

A sequence of serial bits

A C-bit processing circuit of a DAT DSP chip for taking out n bits of m bits consecutive for each bit, comprising: clock generating means for generating first and second bit synchronization clocks synchronized with the serial bit string; (10), successive of the first bit sync clock

Synchronizing signal generating means (20) for generating a synchronizing signal for every two clocks; First clock window means (30) for passing only m consecutive first bit sync clocks among the first bit sync clocks each time the synchronization signal is generated; A counter (40) for counting the m consecutive first bit clocks; Second clock window means (50) for combining each bit output of the counter to pass only a clock synchronized with the n bits of m consecutive m bits of the second bit synchronization clock; A shift register (60) for shifting and storing only bits corresponding to the n second bit synchronous clocks having passed through the second clock window means in the serial bit sequence; And an n-bit register 70 for storing and loading the n bits stored in the shift register in parallel immediately after the clock pass of the first clock window means. Processing circuit.

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